A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology

Kim, M.; Kim, J.; Park, C.; Everson, Luke; Kim, H.; Song, Sang-Bin; Lee, S.; Kim, C. H.

doi:10.1109/iedm.2018.8614599

Cited by 18 publications

(2 citation statements)

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“…[102] As long as the design of the peripheral circuit is implemented appropriately, flash can complete the function of in-memory computing efficiently. [103][104][105] FeFET is a combination of traditional transistors and ferroelectric materials. [106] Due to the spontaneous polarization characteristics of ferroelectric materials, the atoms in the crystal can move over the potential barrier after applying a suitable external field (required to be larger than the coercive field E c ), leading to the inversion of the intrinsic polarization.…”

Section: Charge-based Memorymentioning

confidence: 99%

In-memory computing to break the memory wall*

Huang¹,

Liu²,

Jiang³

et al. 2020

Chinese Phys. B

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Facing the computing demands of Internet of things (IoT) and artificial intelligence (AI), the cost induced by moving the data between the central processing unit (CPU) and memory is the key problem and a chip featured with flexible structural unit, ultra-low power consumption, and huge parallelism will be needed. In-memory computing, a non-von Neumann architecture fusing memory units and computing units, can eliminate the data transfer time and energy consumption while performing massive parallel computations. Prototype in-memory computing schemes modified from different memory technologies have shown orders of magnitude improvement in computing efficiency, making it be regarded as the ultimate computing paradigm. Here we review the state-of-the-art memory device technologies potential for in-memory computing, summarize their versatile applications in neural network, stochastic generation, and hybrid precision digital computing, with promising solutions for unprecedented computing tasks, and also discuss the challenges of stability and integration for general in-memory computing.

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Section: Charge-based Memorymentioning

confidence: 99%

In-memory computing to break the memory wall*

Huang¹,

Liu²,

Jiang³

et al. 2020

Chinese Phys. B

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“…In the past, the planar transistors process technology was used to build logic NVM. 3,4 Recently, advanced process technologies such as FinFET or GAA nanosheet has been or will be adopted in mainstream CMOS. 5,6 Stacked nanosheet or the complementary FET (CFET) structure further improves density of logic NVM.…”

mentioning

confidence: 99%

Nanosheet-Compatible Complementary-Field Effect Transistor Logic Non-Volatile Memory Device

Chang

Chang²,

Lee³

et al. 2022

ECS J. Solid State Sci. Technol.

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This study proposes a logic non-volatile memory (NVM) device based on the state-of-the-art gate-all-around (GAA) nanosheet process. By adopting a complementary field effect transistor (FET) structure, we not only reduce the layout footprint area but also demonstrate the compatibility with sub-3nm nanosheet complimentary metal oxide semiconductor technology. We simulated the device in TCAD for program and erase operations, considering both Fowler Nordheim tunneling and hot carrier injection mechanisms. The memory window is optimized by adjusting the device structure, such as tunneling and blocking oxide thicknesses, top- and bottom-channel width, and the floating gate length, resulting in a significant enhancement in the memory window. Finally, NAND/NOR type CFET logic NVM are demonstrated to reveal the possible applications of gate-all-around stacked junctionless nanosheet transistor towards embedded flash.

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