A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology

Chae, Kwon Seok; Choi, Jongryun; Yi, Shinyoung; Lee, Won; Joo, Sanghoon; Kim, Hyunhyuck; Yi, Hyungkwon; Nam, Yoonjee; Choi, Jeong-Yeol; Park, Sanghune; Lee, Sang‐Hyun

doi:10.1109/esscirc.2016.7598341

Cited by 5 publications

(4 citation statements)

References 2 publications

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“…The compensation block is a Build-In-Self-Test (BIST) method [13]. Compensation operates in the following order: a.…”

Section: Compensation Circuitmentioning

confidence: 99%

“…Because processes differ from process company to process company, general Moore's Law was applied and compared. In [13], the PHY of LPDDR4 was implemented by the Samsung 10 nm process. Compared to this study, the size was small, but considering the process, the size was approximately three times larger.…”

Section: Asic Chipmentioning

confidence: 99%

“…Again, only the PHY was designed, but it was approximately three times larger than that in this study. Although it is difficult to decipher from Table 6, this study, implemented purely digitally, has two advantages in contrast to [13,15]. The first is the time to reach implementation.…”

Section: Asic Chipmentioning

confidence: 99%

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Study on the Implementation of a Simple and Effective Memory System for an AI Chip

Kim¹,

Park

Cho

2021

Electronics

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In this study, a simple and effective memory system required for the implementation of an AI chip is proposed. To implement an AI chip, the use of internal or external memory is an essential factor, because the reading and writing of data in memory occurs a lot. Those memory systems that are currently used are large in design size and complex to implement in order to handle a high speed and a wide bandwidth. Therefore, depending on the AI application, there are cases where the circuit size of the memory system is larger than that of the AI core. In this study, SDRAM, which has a lower performance than the currently used memory system but does not have a problem in operating AI, was used and all circuits were implemented digitally for simple and efficient implementation. In particular, a delay controller was designed to reduce the error due to data skew inside the memory bus to ensure stability in reading and writing data. First of all, it verified the memory system based on the You Only Look Once (YOLO) algorithm in FPGA to confirm that the memory system proposed in AI works efficiently. Based on the proven memory system, we implemented a chip using Samsung Electronics’ 65 nm process and tested it. As a result, we designed a simple and efficient memory system for AI chip implementation and verified it with hardware.

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“…The compensation block is a Build-In-Self-Test (BIST) method [13]. Compensation operates in the following order: a.…”

Section: Compensation Circuitmentioning

confidence: 99%

Section: Asic Chipmentioning

confidence: 99%

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Study on the Implementation of a Simple and Effective Memory System for an AI Chip

Kim¹,

Park

Cho

2021

Electronics

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“…With the advantages of high stability [1][2][3] and strong portability [4][5][6][7], the all digital delay-locked loop (ADDLL) is widely used as multiphase clock generator [8][9][10][11] in double data rate (DDR) synchronous interfaces. The Open NAND Flash Interface Specification (ONFI) [12], which is the industry standard, strictly stipulates the timing requirements of non-volatile double data rate (NV-DDR) high-speed interfaces.…”

Section: Introductionmentioning

confidence: 99%

A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit

et al. 2023

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A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0∘ output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is fabricated in the 0.13 μm CMOS process with a 0.072 mm2 core area. The chip testing results show an operating frequency range from 26 MHz to 1.55 GHz and a typical alignment error of approximately 17 ps.

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Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface

Chae

Koo

et al. 2018

2018 International SoC Design Conference (ISOCC)

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A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology

Cited by 5 publications

References 2 publications

Study on the Implementation of a Simple and Effective Memory System for an AI Chip

Study on the Implementation of a Simple and Effective Memory System for an AI Chip

A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit

Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface

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