A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS

Abstract

This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX. Several analyses and verification techniques, ranging from the clocking architectures for a 40 Gb/s TX to oscillation failures in a two-stage ring oscillator, are addressed in this paper. A tri-state-inverterbased frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed 10 GHz PLL fabricated in the 65 nm CMOS technology occupies an active area of 0.009 mm 2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply. The resulting figure-ofmerit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB. Index Terms-CMOS, jitter, phase-locked loop (PLL), ring oscillator, serial link transmitter.

A 0.11–0.38 pJ/cycle Differential Ring Oscillator in 65 nm CMOS for Robust Neurocomputing

“…Eliminating the restriction of odd number of stages in single ended RO, pseudo differential RO is more flexible since both odd and even stages are allowed. A 4-stage pseudo differential RO [14] is shown in Fig. 1(b).…”

“…Given these requirements, a CMOS ring oscillator (RO) based structure seems like a good choice due to its lowarea and power requirements. To address the third point of robustness, differential ring oscillators should be the preferred topology [14]. In this paper, we propose a new differential delay cell that has reduced number of transistors compared to the conventional one thus reducing energy/cycle due to lower capacitance.…”

Weight Update Generation Circuit Utilizing Phase Noise of Integrated Complementary Metal–Oxide–Semiconductor Ring Oscillator for Memristor Crossbar Array Neural Network‐Based Stochastic Learning

“…The ring oscillators are designed in commercial 45 nm CMOS technology where the nominal supply voltage is 1.0 V. However, 0.5 V supply voltage is used for the ring oscillators to minimize the power consumption at the cost of poor‐phase noise. A two‐stage topology presented by Bae et al is adopted for maximizing the frequency at such low supply voltage. The 1× ring oscillator is designed with the minimum size transistors allowed in the given technology and with a variable load capacitance per stage (8fF–13fF), which is used to tune the frequency.…”

A low power wide tuning range two stage ring VCO with frequency enhancing

“…Voltage controlled oscillator (VCO) is an essential component in modern integrated circuit, such as radio-frequency (RF) transceivers [1,2,3,4,5,6,7,8] and clock data recovery (CDR) systems [9,10,11,12,13,14,15,16,17]. LC VCO has much better jitter performance but limit tuning range.…”

“…LC VCO has much better jitter performance but limit tuning range. LC VCO can expand the tuning range by switched inductors or capacitors [1,9], which really consumes unacceptable area in advanced process. Thus, area efficient ring VCOs are more preferred than LC VCO in advanced CMOS process.…”