A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique

Oh, Dong-Ryeol; Seo, Min-Jae; Ryu, Seung‐Tak

doi:10.1109/jssc.2022.3159569

Cited by 16 publications

(15 citation statements)

References 22 publications

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“…The threshold voltage of comparator is set by the method of resistive voltage division, and the threshold voltages are respectively 1.0V, 1.5V, 2.0V, 2.5V, 3.0V, 3.5V, 4.0V. The delay of comparator is an important target of response speed [26,27]. A latched comparator is used, as shown in Fig.…”

Section: Short Pulse Sampling Circuitmentioning

confidence: 99%

Design of a 5MHz half-bridge gate driver for GaN HEMTs with adaptive output current

Li,

Zhou,

Huang

et al. 2023

IEICE Electron. Express

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In this paper, a half-bridge gate driver with adaptive output current for GaN HEMTs is introduced. The output drive current of the driver is adapted to the load of GaN HEMTs, by adjusting the W/L size of drive transistors. The rise time of driver is achieved to be basically constant by the adaptive output current adjustment for different load, so noise can be effectively immunized and working efficiency is improved. Based on the proposed adaptive output current drive circuit, a halfbridge gate driver is designed and implemented in the 180nm BCD process. Tested results show the driver has a constant rise time of about 5ns under 5MHz with C L of 0.5nF, 2.0nF, and 3.5nF respectively.

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Section: Short Pulse Sampling Circuitmentioning

confidence: 99%

Design of a 5MHz half-bridge gate driver for GaN HEMTs with adaptive output current

Li,

Zhou,

Huang

et al. 2023

IEICE Electron. Express

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show abstract

“…This makes direct sampling receivers [1] [2] very attractive, at the same time placing stringent demands on the analog-to-digital converters (ADCs), which must allow high sampling ratestypically in the range of billions of samples per second (GS/s) -low power consumption, and mid-to-high resolutions. Flash ADCs [3] [4] stand out as the fastest converters among the various available architectures, making them the best choice for high-speed applications. However, they are not power and area-efficient when designed for high or medium-resolution applications.…”

Section: Introductionmentioning

confidence: 99%

A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS

Karrari,

Andreani,

Tan

2024

IEEE Access

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A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successiveapproximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock distribution, a common bootstrapped sampler in front of the four channels is employed. The reset switch in the capacitive digital-toanalog converter (CDAC) of each channel is also bootstrapped to enhance the speed and linearity. A prototype ADC has been designed and implemented in a 22-nm FDSOI CMOS technology, with a core occupation area of 0.43 mm 2 . Measurements show that the ADC achieves a signal-to-noise-and-distortion ratio of 50dB with a low-frequency input, and of 48.5 dB at Nyquist. The total power consumption is 37.5 mW; the core ADC consumes 19.3 mW from a 0.8V supply. With a 1.4 GS/s sampling rate and input at Nyquist, the ADC achieves a Walden's figure of merit of 114 fJ/conversion.INDEX TERMS Analog-to-digital converter (ADC), CMOS, comparator, bootstrapped switch, dynamic amplifier (DA), asynchronous SAR, time-interleaved (TI), pipelined successive approximation (Pipelined-SAR).

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“…In [24], a 7-bit, two-channel, time-interleaved, two-step flash ADC with a speed of 3 GS/s was presented. The ADC has a built-in voltage reference source based on a capacitive DAC and an advanced offset calibration technique.…”

Section: Introductionmentioning

confidence: 99%

New Method for Logarithmic Analogue-to-Digital Conversion Using Switched Capacitors with a Variable Logarithmic Base

Mychuda,

Mykyichuk,

Zhuravel

et al. 2023

Electronics

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This article is devoted to the development of a new method of logarithmic analogue-to-digital conversion using switched capacitors with a variable logarithmic base. The essence of the method and its implementation are presented. Mathematical models have been developed, analysis has been carried out and errors have been assessed. It has been demonstrated that the developed converters, using the proposed method, significantly outperform known analogous converters: for input voltages ranging from 1 mV to 10 V, the processing error does not exceed 0.001% with a processing time not greater than 105 µs (microseconds).

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A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique

Cited by 16 publications

References 22 publications

Design of a 5MHz half-bridge gate driver for GaN HEMTs with adaptive output current

Design of a 5MHz half-bridge gate driver for GaN HEMTs with adaptive output current

A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS

New Method for Logarithmic Analogue-to-Digital Conversion Using Switched Capacitors with a Variable Logarithmic Base

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