A 7-Nm Dual Port 8T SRAM with Duplicated Inter-Port Write Data to Mitigate Write Disturbance

Design and implementation of enhanced lightweight memory-based and monostable physical unclonable functions

“…Random variations can cause a significant mismatch that are largely responsible for the poor yield of the SRAM arrays in scaled technologies [53][54][55]. On the contrary, random variations are desired for PUF application to produce reliable and random response bits.…”

“…Some new optimization strategies in circuit level are investigated in [55] to adequately satisfy the quality requirements for both memory and PUF modes of operation, such as Work-Line Voltage Modulation (WLM), Dynamic Voltage Scaling (DVS), Negative Bit-line (NBL) and Adaptive Body Bias (ABB). Unfortunately, these optimization strategies suffer from increased complexity of the design and added circuit redundancy like the negative voltage generation circuit.…”

“…Common row and common column accesses are inhibited due to the abnormal leakage current flowing through the selected memory cell when complementary data is written to the DP-SRAM. This conflict will not occur when the same data is written to the DP-SRAM cell as show in Table 3.2 [55]. It should be alerted on the stability because the static noise margin of selected cells will be degraded by activating both word-lines together during the read operation.…”