A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step

Harpe, Pieter; Zhang, Yan; Dolmans, Guido; Philips, Kathleen; Groot, Harmke de

doi:10.1109/isscc.2012.6177096

Cited by 69 publications

(43 citation statements)

References 3 publications

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“…Most of the recent low power SAR ADCs with medium resolution use a clocked latch as dynamic comparator [7,17]. But large kick-back noise is only tolerable at fully differential architectures, where both inputs of the latch are driven by equal source impedance.…”

Section: Comparatormentioning

confidence: 99%

“…SAR ADCs reach the highest energy efficiency among all ADC architectures, due to the minimal amount of active circuitry [2], and resolutions up to 12 bit are achieved without calibration. The highly digital nature of SAR ADCs allows implementation in modern CMOS technologies [5,6] and flexible scaling of resolution and conversion rate [7]. Figure 1 illustrates the block level schematic of a classical window ADC, consisting of a set-point DAC to generate the reference voltage, an amplifier for error signal amplification and common-mode shift, and a flash or pipeline ADC with reduced resolution.…”

Section: Introductionmentioning

confidence: 99%

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A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS

Haenzsche

Höppner

Schüffny

2015

Analog Integr Circ Sig Process

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This paper presents a 10 bit charge redistribution successive approximation analog-to-digital converter (ADC) for integrated digitally controlled DC-DC converters. A timing efficient implementation of a window function is proposed, where only a reduced input range is converted. A redundant search is applied to overcome the speed limitation of the analog components. The window mode enables further speed enhancement without an increase of clock frequency and power consumption. Position of the set-point and size of the window is digitally adjustable every conversion. Fabricated in 28 nm low-power CMOS technology the ADC occupies only 110 9 85 lm 2 . In full range mode a conversion rate of 16 MS/s is achieved and in window mode 26.7 MS/s, respectively. With a measured total power consumption of 710 lW and 9.1 bit ENOB a FOM of 81 fJ/conv-step is reached. A large input range with constant resolution, highly linear characteristic, and high robustness to PVT variations together make this ADC an advantageous alternative to delay line or ring oscillator based window ADCs. The highly digital nature of the proposed architecture allows implementation in modern sub-100 nm CMOS technologies.

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Section: Comparatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS

Haenzsche

Höppner

Schüffny

2015

Analog Integr Circ Sig Process

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“…A 9 bit DAC is sufficient for a 10 bit ADC as the LSB bit cycle doesn't need to update the DAC anymore. An additional capacitor of 32 C is inserted to add redundancy, which relaxes DAC settling requirements and saves comparator power [9]. The DAC is implemented based on custom designed capacitors which utilize the parasitic fringing capacitance between 3 different metal layers (metal layers 3, 4, and 5 are placed in parallel to increase capacitor density while metal layer 1 is placed underneath for shielding).…”

Section: B Power-efficient Data Conversionmentioning

confidence: 99%

“…In both ECG and FE channels, the signals are converted into single-ended at the PGA stage to reduce the power consumption by driving a single-ended ADC. In addition to that, the 7 b-to-10 b configurable ADC [9] digitizes ECGout and FEout via a current-multiplexed (CMPX) buffer to avoid the use of power-consuming channel buffers and ADC drivers.…”

Section: Introductionmentioning

confidence: 99%

A 680 nA ECG Acquisition IC for Leadless Pacemaker Applications

Yan

Harpe

Pamula

et al. 2014

IEEE Trans. Biomed. Circuits Syst.

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Abstract-A sub-ECG acquisition IC is presented for a single-chamber leadless pacemaker applications. It integrates a low-power, wide dynamic-range ECG readout front end together with an analog QRS-complex extractor. To save ASIC power, a current-multiplexed channel buffer is introduced to drive a 7 b-to-10 b self-synchronized SAR ADC which utilizes 4 fF/unit capacitors. The ASIC consumes only 680nA and achieves CMRR 90 dB, PSRR 80 dB, an input-referred noise of 4.9 in a 130 Hz bandwidth, and has rail-to-rail DC offset rejection. Low-power heartbeat detections are evaluated with the help of the ASIC acquiring nearly 20,000 beats across 10 different records from the MIT-BIH arrhythmia database. In the presence of muscle noise, both the average Sensitivity (Se) and Positive Predictivity (PP) show more than 90% when the input SNR 6 dB.

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“…For those reasons, it is difficult to use high-performance amplifiers and analog filters that have a high quality factor. Ultra-low-power ADCs, which have sub-microwatt power consumption and a limited sample rate, have been developed for biomedical applications [9], [10]. Furthermore, according to Moore's law, the power of digital components increases with the progress of process technology.…”

Section: Introductionmentioning

confidence: 99%

Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems

Izumi

Yamashita

Nakai

et al. 2015

IEICE Trans. Inf. & Syst.

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SUMMARYThis report describes a robust method of instantaneous heart rate (IHR) extraction from noisy electrocardiogram (ECG) signals. Generally, R-waves are extracted from ECG using a threshold to calculate the IHR from the interval of R-waves. However, noise increases the incidence of misdetection and false detection in wearable healthcare systems because the power consumption and electrode distance are limited to reduce the size and weight. To prevent incorrect detection, we propose a short-time autocorrelation (STAC) technique. The proposed method extracts the IHR by determining the search window shift length which maximizes the correlation coefficient between the template window and the search window. It uses the similarity of the QRS complex waveform beat-by-beat. Therefore, it has no threshold calculation process. Furthermore, it is robust against noisy environments. The proposed method was evaluated using MIT-BIH arrhythmia and noise stress test databases. Simulation results show that the proposed method achieves a state-of-the-art success rate of IHR extraction in a noise stress test using a muscle artifact and a motion artifact.

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A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step

Cited by 69 publications

References 3 publications

A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS

A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS

A 680 nA ECG Acquisition IC for Leadless Pacemaker Applications

Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems

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