A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer

Abstract

This paper presents a 700-MS/s 6-bit SAR ADC with a novel on-chip reference voltage buffer in a 40-nm CMOS Low-Leakage (LL) process. The reference voltage buffer is partially active depending on the operation state of the SAR ADC. The large driving current is provided only when the Capacitive Digital-to-Analog Converter (CDAC) is settling. This approach achieves 42% power reduction for the reference voltage buffer, which helps to improve the Figure-

A 10-bit 120MS/s SAR ADC using tri-switch sampling and VCM-stable switching scheme in 40-nm CMOS

“…Over the course of several decades, some ADC architectures have been developed and widely used, such as flash [1,2,3], pipeline [4,5,6], sigma-delta [7,8], SAR [9,10,11,12], and interleaved [13,14,15] ADCs. Each owns specific characteristics in terms of sample rate, accuracy, etc.…”