A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range

A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS

“…If the clock jitter is removed, the ADC achieves an ERBW over 100 MHz and the FOM is 6.95 fJ/Conversion-step. Table II compares the proposed ADC with other state-ofthe-art non-interleaved SAR ADCs [1][2][3][4]. The proposed SAR ADC shortens the digital logic delay and tolerates the incomplete settling error without additional conversion cycle.…”

“…Therefore, power efficiency of the SAR architecture surpassed the pipelined architecture in deep sub-micron process. Recent publications show SAR ADCs with medium resolution (8~12b) and several tens MS/s [1][2][3][4]. This paper manipulates the bypass window [5], direct switching technique, and small unit capacitor to enhance the conversion speed up to 200 MS/s for a single channel 10b SAR ADC with 0.818 mW power consumption.…”

A 1-V–0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry

“…Note that the AFE in Fig. 1 [7] rely on passive charge-sharing (CS) instead of active charge-redistribution during DAC feedbacks. The reference voltage is firstly sampled into reference charge (Q ref ) before the conversion actually commences.…”

“…Similarly for the reference bouncing related to the Q ref refueling instance, the sampled Q ref also remains constant regardless of the fluctuations by the sampling coherency. Moreover, CS-SAR ADCs can also have a high dynamic range of 70 dB as demonstrated in [7]. The input buffer is relaxed to a simple transconductor instead of a high-GBW, fast-settling, feedback OPAMP [5]- [7].…”

“…Moreover, CS-SAR ADCs can also have a high dynamic range of 70 dB as demonstrated in [7]. The input buffer is relaxed to a simple transconductor instead of a high-GBW, fast-settling, feedback OPAMP [5]- [7]. An embedded sinc frequency response is enjoyed due to the BOXCAR integration sampling, consequently loosening up the anti-aliasing filtering preceding the ADC.…”