A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors

Zhang, Minglei; Cao, Yuefeng; Zhu, Yan; Chan, Chi-Hang; Martins, Rui P.

doi:10.23919/vlsitechnologyandcir57934.2023.10185416

Cited by 6 publications

(1 citation statement)

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“…Compared to the proposed ADC, the ADC in [4] features a similar resolution and sampling rate but it lacks the calibration circuit, which is implemented in an off-chip FPGA. Due to the use of a pipeline-SAR structure, the sampling rate of the ADCs presented in [24,25] is higher, but the proposed ADC has a higher resolution and SNDR. ADC achieves competitive SNDR and SFDR after calibration.…”

Section: Simulation Resultsmentioning

confidence: 99%

A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

He,

Qiao,

Xing

et al. 2024

JLPEA

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A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology.

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Section: Simulation Resultsmentioning

confidence: 99%