A 79-dB SNR 1.1-mW Fully Integrated Hearing Aid SoC

A Survey on Application Specific Processor Architectures for Digital Hearing Aids

“…An alternative approach to linearly constrained adaptive beamforming [20] Beamforming (BMF) [41,56] 1984 Speech enhancement using a minimum-mean square error short-time spectral amplitude estimator [14] Speech enhancement (SE) [5] 1985 Speech enhancement using a minimum mean-square error log-spectral amplitude estimator [15] Noise reduction (NR) [9] 1995 Noise estimation techniques for robust speech recognition [23] Noise reduction (NR) [56] 1996 Speech enhancement based on a priori signal to noise estimation [59] Speech enhancement (SE) [56] 1997 Comparison of voice activity detection algorithms for wireless personal communications systems [13] Voice Activity Detector (VAD) [65] 1997 Adaptive digital filter in subbands: Design issues and experimental results for acoustic echo cancellation [16] Feedback cancellation (FBC) [33] 1999 A novel approach of adaptive feedback cancellation for hearing aids [10] Feedback cancellation (FBC) [9,25] 2001 First-and second-order adaptive differential microphone arrays [68] Adaptive directional microphone (ADM) [3] 2001 Hearing aid digital filter [66] Digital filter [17, 30-32, 65, 74] 2001 Assessing local noise level estimation methods: Application to noise robust ASR [58] Noise reduction (NR) [5] 2002 Digital envelope detector for blood pressure measurement using an oscillometric method [38] Adaptive SNR Monitor [74] 2002 An improved entropy-based endpoint detection algorithm [24] Voice Activity Detector (VAD) [72] 2002 A multi-band spectral subtraction method for enhancing speech corrupted by colored noise [27] Noise reduction (NR) [9,25,33] 2002 Adaptive Null-Forming Scheme in Digital Hearing Aids…”

“…Hard-wired architectures offer a comparatively low-power consumption compared to the ASIP architectures. The power distribution for the hardware components of the mixed-signal hearing aid [5] is 36% for the analog front end, 39% for the digital signal processor (DSP), 11% for the power on reset circuit and 13% for the remaining components. The digital signal processor of the hearing aid presented in [9], on the other hand, consumes up to 71%, while the analog parts consume the remaining 29%.…”

“…An implementation of a related noise reduction algorithms (mband) on an ASIP with hardware accelerators [33] needs 2176 cycles for computation. Parallelism at data or instruction level, or application-specific instructions [4,5,9,19,25,33,35,47,51,56] can reduce the clock frequency requirement. Accelerators are used for computing intensive tasks, where the pure software implementation on an ASIP is not feasible.…”

A Smart Binaural Hearing Aid Architecture Leveraging a Smartphone APP With Deep-Learning Speech Enhancement

“…Table 6 presents the four types of HA: conventional HA [49], a wireless binaural HA [50], a smartphone-based HA system [27], and the proposed structure. Reference [49] was a mixedsignal system, and the rest are based on digital circuit design. The [27], [49] is a monaural HA, and the rest are binaural HAs.…”

“…Reference [49] was a mixedsignal system, and the rest are based on digital circuit design. The [27], [49] is a monaural HA, and the rest are binaural HAs. Speech signal processing is done on the HA side for the other systems, but for the architecture we proposed, it was done on the smartphone.…”