A 7nm 4GHz Arm<sup>®</sup>-core-based CoWoS<sup>®</sup> Chiplet Design for High Performance Computing

Lin, Mu-Shan; Huang, Tze-Chiang; Tsai, Chien‐Hsiung; Tam, King-Ho; Hsieh, Cheng-Hsiang; Huang, Wen-Hung; Hu, Jack; Goel, Sandeep; Fu, Chin-Ming; Rusu, Stefan; Li, Chao-Chieh; Yang, Shixuan; Wong, Mei; Yang, Shuo; Lee, Frank

doi:10.23919/vlsic.2019.8778161

Cited by 35 publications

(6 citation statements)

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“…We target a wireless chiplet-based architecture employing four instances of a state-of-the-art chiplet design [20], each with a 4-core cluster and shared L2 and L3 caches. The system elements are configured as shown in Table I.…”

Section: Methodsmentioning

confidence: 99%

REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal

Medina,

Huang,

Ansaloni

et al. 2023

2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)

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2.5D Systems-on-Package (SoPs) are composed by several chiplets placed on an interposer. They are becoming increasingly popular as they enable easy integration of electronic components in the same package and high fabrication yields. Nevertheless, they introduce a new bottleneck in inter-chiplet communication, which must be routed through the interposer. Such a constraint favors mapping related tasks on computing cores within the same chiplet, leading to thermal hotspots. Inpackage wireless technology holds promise to reconsider such a position because integrated wireless antennas provide low-latency and high-bandwidth communication paths, thus bypassing the interposer bottleneck. Furthermore, in this work, we propose a new task mapping heuristic that leverages in-package wireless technology to improve the thermal behavior of 2.5D SoPs executing complex applications. Combining system simulation and thermal modeling, our results show that we can distribute computation in wireless 2.5D SoPs to reduce peak temperatures by up to 24% through task mapping with a negligible performance impact.

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Section: Methodsmentioning

confidence: 99%

REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal

Medina,

Huang,

Ansaloni

et al. 2023

2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)

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“…据不完全统计, 目前已有不下 1000 种电子封装集成技术, 较具代表性的除前述 MCM, SiP 外, 还有近年 TSMC 推出并持续发展的先进集成芯片系统 (system on integrated chips, SoIC) 等 [14,15] . 电子封装集成技术按照集成维度可分为两大类, 即二维封装集成技术和基于 Z 轴延伸的三维封装集成技术 [16] .…”

Section: 吴林晟等: 从集成电路到集成系统unclassified

From integrated circuits to integrated systems

WU,

MAO

2023

Sci. Sin.-Inf.

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“…From the viewpoint of electron packaging applications, the design concept of chiplet arrangement was proposed to improve the yield and reduce product costs [ 27 , 28 ]. A dual-chiplet, interposer-based system-in-package architecture was demonstrated to establish a high-performance computing processor design, and the data rate of up to 8 Gb/s with relatively low power and area overhead was explored [ 29 ]. The development and manufacturing cost of AMD’s 32-core CPU was reduced by 40% because of the chiplet design; this performance revealed its advantage in cost reduction [ 30 ].…”

Section: Introductionmentioning

confidence: 99%

Layout Dependence Stress Investigation in through Glass via Interposer Architecture Using a Submodeling Simulation Technique and a Factorial Design Approach

et al. 2023

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The multi-chiplet technique is expected to be a promising solution to achieve high-density system integration with low power consumption and high usage ratio. This technique can be integrated with a glass interposer to accomplish a competitive low fabrication cost compared with the silicon-based interposer architecture. In this study, process-oriented stress simulation is performed by the element activation and deactivation technique in finite element analysis architecture. The submodeling technique is also utilized to mostly conquer the scale mismatch and difficulty in mesh gridding design. It is also used to analyze the thermomechanical responses of glass interposers with chiplet arrangements and capped epoxy molding compounds (EMC) during curing. A three-factor, three-level full factorial design is applied using the analysis of variance method to explore the significance of various structural design parameters for stress generation. Analytic results reveal that the maximum first principal stresses of 130.75 and 17.18 MPa are introduced on the sidewall of Cu-filled via and the bottom of the glass interposer, respectively. Moreover, the EMC thickness and through glass via pitch are the dominant factors in the adopted vehicle. They significantly influence the stress magnitude during heating and cooling.

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A 7nm 4GHz Arm^®-core-based CoWoS^® Chiplet Design for High Performance Computing

Cited by 35 publications

References 0 publications

REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal

REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal

From integrated circuits to integrated systems

Layout Dependence Stress Investigation in through Glass via Interposer Architecture Using a Submodeling Simulation Technique and a Factorial Design Approach

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A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing

Cited by 35 publications

References 0 publications

REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal

REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal

From integrated circuits to integrated systems

Layout Dependence Stress Investigation in through Glass via Interposer Architecture Using a Submodeling Simulation Technique and a Factorial Design Approach

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Product

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A 7nm 4GHz Arm^®-core-based CoWoS^® Chiplet Design for High Performance Computing