A 8.2-pW 2.4-pA Current Reference Operating at 0.5 V With No Amplifiers or Resistors

Zhuang, Haoyu; Guo, Jinfeng; Tong, Can; Peng, Xizhu; Tang, He

doi:10.1109/tcsii.2019.2936874

Cited by 14 publications

(14 citation statements)

References 29 publications

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“…A second category uses the ratio of a temperature-dependent voltage whose TC matches the one of the resistance. It can be achieved by (i) a slightly PTAT voltage buffered by a linear regulator [42], (ii) a CTAT voltage buffered by a single transistor [9], or (iii) a voltage matching the 1 st and 2 nd order TCs of a polysilicon resistor [7]. This type of current reference can easily be calibrated to reach a competitive TC performance by matching the 1 st order TC of the resistance, but usually relies on an operational amplifier to buffer the reference voltage onto the resistor, and can lead to rather complex voltage generator architectures if 2 nd order TC matching is required.…”

Section: B Cwt Current Reference Topologiesmentioning

confidence: 99%

“…2(a) relies on a CWT voltage reference biasing a gate-leakage transistor, which acts as a resistance in the order of GΩ. This structure was proposed in [8], [9] and generates a CWT reference current in the pA range. Second, the current reference in Fig.…”

Section: B Cwt Current Reference Topologiesmentioning

confidence: 99%

“…2(d) summarizes the characteristics of the three references described hereabove. In the remainder of this paper, we focus on the nA-and µA-range current reference topologies, as the pA-range one has already been proposed in previous art [8], [9]. The topology brought forward in this work offers three main advantages.…”

Section: B Cwt Current Reference Topologiesmentioning

confidence: 99%

“…On the other hand, current references remain more complex than their voltage counterparts, often requiring more components and an intricate sizing [7]. Nonetheless, recent works have shown that a 2T voltage reference can be used to generate a reference current once replicated onto a gate-leakage transistor by a 1T buffer [8], [9]. Such works suggest that simpler yet competitive architectures are within reach.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we build upon [8], [9] to create a family of simple current references without startup circuit sharing two key principles: (i) the generation of a voltage reference by a 2T ULP structure and (ii) its buffering by a single transistor onto a voltage-to-current (V-to-I) converter. Compared with [8], [9], we substitute the gate-leakage transistor by either a self-cascode MOSFET (SCM) or a resistor, respectively resulting in a nA-and µA-range current. This leads to two novel current reference topologies, fabricated in a 0.18-µm partially-depleted silicon-on-insulator (PDSOI) process.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-$μ$m with 0.1-nA PTAT and 1.1-$μ$A CWT 38-ppm/$^\circ$C Designs

Lefebvre,

Bol

2022

Preprint

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The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18-µm partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolutetemperature (PTAT) reference intended for constant-gm biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/ • C, and a variability (σ/µ) of 1.66 %. Then, two 4T+1R µA-range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09-µA (resp. 0.99-µA) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/ • C (resp. 290-ppm/ • C) TC, and a 0.87-% (resp. 0.65-%) (σ/µ). In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations.

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Section: B Cwt Current Reference Topologiesmentioning

confidence: 99%

Section: B Cwt Current Reference Topologiesmentioning

confidence: 99%

Section: B Cwt Current Reference Topologiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-$μ$m with 0.1-nA PTAT and 1.1-$μ$A CWT 38-ppm/$^\circ$C Designs

Lefebvre,

Bol

2022

Preprint

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pMOS‐only pW‐power voltage reference with sub‐10 ppm/°C trimmed temperature coefficient and sub‐100 ppm/V line sensitivity

Azimi

Habibi

Crovetti

2023

Circuit Theory & Apps

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In this paper, a new ultra-low-power voltage reference based on a two-stage, all-pMOS topology operating in the subthreshold region is proposed to uniquely meet the pW-power range power consumption requirements of emerging Internet-of-Things applications without significantly compromising the temperature coefficient (TC) and the line sensitivity (LS) performance. The proposed circuit consists of the LS regulator, TC corrector, and TC trimming sections. Based on post-layout Monte Carlo simulations in 180-nm CMOS, the proposed circuit operates with 0.8-to 2.4-V supply potential and generates a reference voltage of 206 mV with a process spread of 7.8%, achieving an average calibrated TC of 4.4 ppm/ C in the temperature range of À20 C to 80 C, and an average LS of 51.5 ppm/V with a power consumption of 25.9 pW at 25 C (469.1 pW at 80 C).

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Low-power filter design using quasi-floating gate and level shifter approaches for biological healthcare applications

Thakur,

Sharma

2024

AEU - International Journal of Electronics and Communications

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A 8.2-pW 2.4-pA Current Reference Operating at 0.5 V With No Amplifiers or Resistors

Cited by 14 publications

References 29 publications

A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-$μ$m with 0.1-nA PTAT and 1.1-$μ$A CWT 38-ppm/$^\circ$C Designs

A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-$μ$m with 0.1-nA PTAT and 1.1-$μ$A CWT 38-ppm/$^\circ$C Designs

pMOS‐only pW‐power voltage reference with sub‐10 ppm/°C trimmed temperature coefficient and sub‐100 ppm/V line sensitivity

Low-power filter design using quasi-floating gate and level shifter approaches for biological healthcare applications

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