A 80 Mb/s low-power scalable turbo codec core

Giulietti, Alexandre; Bougard, Bruno; Derudder, Veerle; Dupont, Steven; Weijers, Jan-Willem; Perre, Liesbet Van der

doi:10.1109/cicc.2002.1012851

Cited by 23 publications

(12 citation statements)

References 7 publications

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“…We have implemented a turbo codec ASIC based on the propose d archit ecture [26]. VHDL code was written to model at RTL level the functionality of the encoder and turbo-decoder.…”

Section: Resultsmentioning

confidence: 99%

Turbo Coding for 4G Systems: Design Issues and Solutions

Giulietti¹,

Strum²,

Bougard³

et al. 2003

Journal of Communication and Information Systems

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-After the initial interest caused by the appearance of turbo codes in 1993. special attention on the implementation has Jed to their adoption in some of the most important 3G standards. However. future broadband systems (with data rates up to 155 Mbis) still require a better speed/latency/power performance than those found in current implementations. This paper discusses several design aspects of a broadband. low-power turbo codec owning features that enable its application in the incoming decade systems. The presented ideas were applied to an 80 Mb/s, 2 nJ/bit turbo codec core with latency smaller than 10ms. This flexible architecture allows re-scaling towards faster low power implementations (beyond I Gb/s).Keywords: Turbo codes. VLSI. low-power. broadband. Resumo -Ap6s 0 interesse inicial causado pelo surgimento dos c6digos turbo em 1993. uma atencao especial para a implernentacao levou a sua utilizacao em alguns dos mais importantes padroes 3G. Entretanto. os futuros sistemas de faixa larga (com taxas de dados de ate 155Mb/s) requerem um desempenho de velocidade/latencia/potencia ainda melhor do que aquele encontrado nas atuais implementacoes. Esse artigo discute diversos aspectos de projeto de um codec turbo de baixa potencia cujas caracteristicas possibilitam a sua aplicacao nos sistemas da proxima decada, As ideias apresentadas foram aplicadas a urn codec turbo operando a 80 Mb/s e 2nJ/bit com latencia menor do que lOms. Essa arquitetura Hexi vel permite reescalonamento. na direcao de se ter implernentacoes de mais baixa poiencia e mais rapidas (acima de I Gb/s).Palavras-chave: C6digos turbo, VLSL baixa potencia, faixa larga.

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“…We have implemented a turbo codec ASIC based on the propose d archit ecture [26]. VHDL code was written to model at RTL level the functionality of the encoder and turbo-decoder.…”

Section: Resultsmentioning

confidence: 99%

Turbo Coding for 4G Systems: Design Issues and Solutions

Giulietti¹,

Strum²,

Bougard³

et al. 2003

Journal of Communication and Information Systems

Self Cite

View full text Add to dashboard Cite

show abstract

“…The latency of the sequential architecture is that of the decoding unit (10) The latency consists of the delay of the practical SISO due to prior input of five windows ( for the algorithm with tailbiting termination) in addition to processing metrics of the block, all multiplied by the number of iterations.…”

Section: Sequential Decoder Architecturementioning

confidence: 99%

“…However, the algorithms proposed there did not apply a sliding window inside subblocks. The technique proposed here creates boundary metrics for the first and last subblocks using the same process as for the other subblocks, thus differing from [10]- [12], and causing no performance degradation nor increasing the computational load.…”

Section: Parallel Decoder Architecturementioning

confidence: 99%

“…Those schemes trade off the number of SISOs for error correction performance, and are reported as having increased hardware complexity relative to sequential architectures. The designs presented in [9] and [10], and the architectures presented in [11] and [12], employ the sliding window approach inside each subblock that is decoded in parallel. In our approach [13], the subblocks are processed in a similar way, while the definitions of the boundary metric values for the beginning and the end of the block are improved by use of tailbiting termination.…”

Section: Introductionmentioning

confidence: 99%

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Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

Dobkin

Peleg

Ginosar

2005

IEEE Trans. VLSI Syst.

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Abstract-Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent SISO outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times and throughput for large blocks is increased up to six-fold relative to sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area.Index Terms-Decoders, interleaver, maximum a posteriori (MAP) algorithm, parallel architecture, turbo codes, VLSI architecture.

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“…The turbo encoder energy consumption is computed by adding one memory write and read operation per hit to the corresponding convolutional encoder, to take the interleaver into account, above the two convolutional encoders. Besides this first estimation, we also consider a lowpower and low-latency optimized implementation of a turbo codec [7]. Selecting the best parameters in order to maximize the coding gain, we can reach a BER of for an Eb/Nu value of 2.9 dB with rate 112 and 2.5 dB with rate 1/3.…”

Section: F R R B O Codesmentioning

confidence: 99%

Selection of channel coding for low-power wireless systems

Desset

Fort

The 57th IEEE Semiannual Vehicular Technology Conference, 2003. VTC 2003-Spring.

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The wireless communications world is moving towards the so-called 4 6 picture, by integrating many different subsystems. Some of them have t o provide short-range connectivity at very low power, in order t o enable hatteryopdrated sensors or devices. This low-power requirement can be achieved by selecting channel codes of high coding gain, However, the power consumption of encoding and decoding operations also has t o be taken into account. This paper analyzes this trade-off between coding gain and digital power consumption, considering different wireless scenarios. It shows that turbo codes can be used even for relatively low-power applications. For very low-power systems, simple Hamming codes provide a good trade-off, as well as convolutional codes. The Golay code is another strong candidate, thanks to a very efflcient implementation. Considering current CMOS technology, the different codes are in competition for systems sending bits with an energy between 0.1 and 10 nJ. Systems working at lower values do not gain anything in coding, while systems working above will always advantageously use turbo-codes.

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A 80 Mb/s low-power scalable turbo codec core

Cited by 23 publications

References 7 publications

Turbo Coding for 4G Systems: Design Issues and Solutions

Turbo Coding for 4G Systems: Design Issues and Solutions

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

Selection of channel coding for low-power wireless systems

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