A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs

Suanes, Alejandro; Dei, Michele; Terés, Lluís; Serra-Graells, F.

doi:10.1016/j.vlsi.2022.02.002

Search citation statements

Order By: Relevance

Paper Sections

Select...

Mdac Block1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2023

2024

Publication Types

Select...

Article4

Relationship

Self Cite0

Independent4

Authors

Journals

Cited by 4 publications

(1 citation statement)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The bootstrapped switch connects the feedback capacitor to the MDAC output and transfers the input signal to the MDAC block. As shown in Figure 11(b), the bootstrapped switch uses a capacitor to stabilize the VGS of the primary switch transistor (Q7) [26], [27].…”

Section: Mdac Blockmentioning

confidence: 99%

The 1.5 bit-per-stage 10-bit pipelined CMOS A/D converter for CMOS image sensor

Menssouri,

El Khadiri,

Tahiri

2023

IJPEDS

View full text Add to dashboard Cite

<span lang="EN-US">This paper presents a 1.5-bit/stage pipeline analog-to-digital converters (ADC) with a 100 MHz operating frequency for CMOS image sensors built using TSMC 90nm CMOS technology. The design features a novel architecture including a comparator, CMOS transmission gates, a sub-ADC logic circuit, bootstrap switches, and a gain-boosted fully differential telescopic op-amp based switched-capacitor MDAC. The ADC operates on a 1.8 V power supply, with a typical power dissipation of 1.632 mW, and a full-scale input signal voltage of 0.8 V. At 100 MHz sampling frequency, it achieves a maximum ENOB of 12.42 bits, an SNR of 76.53 dB, and a FOM of 0.297 pJ/conversion step. This 1.5-bit/stage pipeline ADC is well-suited for CMOS image sensors.</span>

show abstract

Section: Mdac Blockmentioning

confidence: 99%