2021
DOI: 10.12928/telkomnika.v19i2.18318
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A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system

Abstract: In wireless implantable systems (WIS) low power consumption and linearity are the most prominent performance metrics in data acquisition systems. successive approximation register-analog to digital converter (SAR-ADC) is used for data processing in WIS. In this research work, a 10-bit low power high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC architecture is designed using the sample and hold (S/H) circuit consisting of a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latc… Show more

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Cited by 4 publications
(4 citation statements)
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“…In the double bootstrap switch, the gate-source voltage is raised to twice the supply voltage. Also, the bootstrap switch followed by a dummy switch is used [3,4] for the clock feed through compensation. Te charge injected during conversion is compared with the charge induced by a dummy switch.…”
Section: Sar Sample and Hold Circuitmentioning
confidence: 99%
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“…In the double bootstrap switch, the gate-source voltage is raised to twice the supply voltage. Also, the bootstrap switch followed by a dummy switch is used [3,4] for the clock feed through compensation. Te charge injected during conversion is compared with the charge induced by a dummy switch.…”
Section: Sar Sample and Hold Circuitmentioning
confidence: 99%
“…Due to their lowest number of transistors, this scheme saves both power and area. Te basic structure of the single-stage dynamic latch comparator [3,4,6,16,63,86,94] is presented in Figure 5. It consists of three sections, including the diferential amplifcation section (M1 and M2), the cross-coupled inverter section (M3:M6), and the reswitched section (S1:S4).…”
Section: Single-stage Dynamic Latchmentioning
confidence: 99%
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