A 1 MEGA word by l b DRAM assembled into an 18-pin 300-mil plastic DIP with quasi-four-bit-wide test capability will be described. and fine patterning t o realize a slim dc accomodated to the 300-mil plastic DIP; Figure 1.A 1.Opdesign rule requires the use of double level polycide technology, because polycide is more suitable than aluminum for making fine patterns. In other words, polycide allows the use of reflow technique that planarizes the insulator layer underneath the fine aluminum interconnections.The double level polycide, the first layer for MOSFETs gate electrode and the second layer for source/drain interconnection, provides a high performance MOSFET, reducing parasitic resistance and capacitance associated with a photomask design. The double-level polycide technology allows the design of compact peripheral circuits, which are connected with shrinking memory cell, 3 . 4~~ 6 . 0~ with 60fF trench capacitor'.1 ohm/o. The resistivity allows the second layer to be used as a part of Vcc/Vss interconnection, instead of aluminum. This double level polycide structure provides an optimized photo mask design similar to the double level aluminum approach", and contributes to the making of a slim die. The die size measures 4.6mm x 9.4mm. The cross sectional topology of the double level polycide structure is shown in Figure 2.A microphotograph of the DRAM is shown in Figure 3. The RAM has four memory cell blocks, divided with a row/column decoder band, with a sense amplifier band located at the center of each block. Another feature of this DRAM is rapid testing time. As the The 1Mb DRAM must employ double level interconnectionsEach layer consists of TiSi, whose sheet resistivity is below memory capacity per chip increases, the time for testing will grow rapidly. A test time panic is predicted at 1Mb. Thus, the quasi-four-bit-wide test circuit has been employed to reduce testing time.a voltage beyond Vcc to the NC pin reforms the internal organization of the DRAM. During normal operation, the pin is allowed to stay at any state. operation cause the switches to open independently from a An NC pin was used to specify the test mode. Application of In the test mode, sequential data switches for nibble mode ~ Mb Dynamic MOS Memories", IEDM Technical Digest, p. 806-'Sunami, T., et. al., "A Corrugated Capacitor Cell (CCC) f o r 8 0 8 ; Dec., 1984. 'Fujii, T., et. al., "A 90ns 256K x l b DRAM with Double-Level AI Technology", IEEE Journal or Solid-state Circuits, P. 437-440: Oct., 1983.nibble decoder state. Thus, input data are written to each of four blocks simultaneously. The readout data appear on a normal DOUT terminal and three different address terminals, respectively. These operating waveforms are shown in Figure 4.The RAM can be operated as a 256K x 4b DRAM, with addreos/out common. This halves the testing time, compared t o the conventional organization. Since defects in memory cells are the main reason of device failures, this testing method is sufficient for rejecting failures. as its circuit has utilized four da...
