A 900 MS/s 6b interleaved CMOS flash ADC

Yu, Boyang; Black, W.C.

doi:10.1109/cicc.2001.929744

Cited by 16 publications

(7 citation statements)

References 3 publications

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“…The distinguishing feature of the TIQ ADC from the other flash ADCs [1,3,4,7] is the use of CMOS inverters as voltage comparators. Figure 1 shows both the conventional flash ADC and the TIQ ADC.…”

Section: The Tiq Adcmentioning

confidence: 99%

A power and resolution adaptive flash analog-to-digital converter

Yoo

Lee

Choi

et al. 2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design - ISLPED '02

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A new power and resolution adaptive flash ADC, named PRA-ADC, is proposed. The PRA-ADC enables exponential power reduction with linear resolution reduction. Unused parallel voltage comparators are switched to standby mode. The voltage comparators consume only the leakage power during the standby mode. The PRA-ADC, capable of operating at 5-bit, 6-bit, 7-bit, and 8-bit precision, dissipates 69 mW at 5-bit and 435 mW at 8-bit. The PRA-ADC was designed and simulated with 0.18 µm CMOS technology. The PRA-ADC design is applicable to RF portable communication devices, allowing tighter management of power and efficiency.

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Section: The Tiq Adcmentioning

confidence: 99%

A power and resolution adaptive flash analog-to-digital converter

Yoo

Lee

Choi

et al. 2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design - ISLPED '02

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show abstract

“…The TIQ ADC is a flash ADC which consists of 2 n − 1 voltage comparators and 2 n bit to n bit encoder. The distinguishing feature of the TIQ ADC from the other flash ADCs [1,3,4,7] is the use of CMOS inverters as voltage comparators. Figure 1 shows both the conventional flash ADC and the TIQ ADC.…”

Section: The Tiq Adcmentioning

confidence: 99%

A power and resolution adaptive flash analog-to-digital converter

Yoo¹,

Lee²,

Choi³

et al. 2002

Proceedings of the International Symposium on Low Power Electronics and Design

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A new power and resolution adaptive flash ADC named PRA-ADC, is proposed. The pRA-ADC enables tial power reduction with linear resolution reduction, u nused parallel voltage comparators are switched to standby mode. The voltage comparators consume only the leakge power during the standby mode. The PRA-ADC, capable of operating at 5-bit, g-bit, 7-bit, and 8-bit precision, dissipates 69 m~ at 5-bit and 435 mW at 8-bit. The PRA-ADC was designed and simulated with 0.18 pm CMOS technology. nication devices, allowing tighter management of power and efficiency.has been fabricated. Of course, one can use only 6-bit precision from an 8-bit ADC chip, while full 8-bit operation takes place internally. Such an application is non-optimal, resulting in slower speed and extra power consumption due to full 8-bit internal operation. This proposition applies t o the flash which are parallel high-speed high-power A new flash ADC design is proposed in this paper, a true variable power and variable resolution ADC. It is named Power and Resolution Adaptive ADC (PRA-ADC). PRApower when it Operates at a lower ADC feature is highly desirable in many wireless mobile applications. For example, the strength of a radio frequencyThe PRA-ADC design is applicable to R F portable commu-ADC can 'perate at higher speed and will less The

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“…Flash ADCs [8], [9], [10], also known as parallel ADCs, provide the fastest conversion of analog signals into digital signals. Flash ADCs are suitable for applications that require extremely high bandwidths.…”

Section: Introductionmentioning

confidence: 99%

The design of a10-Gsps analog-to-digital converter board for the radio astronomy community

Jiang

Liu

Guzzino

2014

2014 IEEE 23rd International Symposium on Industrial Electronics (ISIE)

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A 4-bit, 10 gigasamples per second (Gsps) analog-to-digital converter (ADC) printed circuit board (PCB) was designed and manufactured for digitizing radio telescopes. Associated with the field-programmable gate array (FPGA) platform developed by the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER) community, the developed PCB provides data acquisition systems with a wider bandwidth and simplifies the intermediate frequency (IF) section. The wider ADC bandwidth enables down converters in the IF section to be simplified, thereby saving resources. The current version of the PCB possesses an analog bandwidth of up to 5.9 GHz, whereas the chip possesses an analog bandwidth of to 18 GHz. This facilitates second and third Nyquist sampling using the revised PCB. Index Terms: analog-to-digital converter (ADC), fieldprogrammable gate array (FPGA)

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A 900 MS/s 6b interleaved CMOS flash ADC

Cited by 16 publications

References 3 publications

A power and resolution adaptive flash analog-to-digital converter

A power and resolution adaptive flash analog-to-digital converter

A power and resolution adaptive flash analog-to-digital converter

The design of a10-Gsps analog-to-digital converter board for the radio astronomy community

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