A 90nm CMOS Variable-Gain Amplifier and RSSI Design for Wide-band Wireless Network Application

Teo, T. Hui; Arasu, Muthukumaraswamy Annamalai; Yeoh, Wooi Gan; Itoh, M.

doi:10.1109/esscir.2006.307537

Cited by 19 publications

(13 citation statements)

References 7 publications

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“…In particular, we study a typical front end consisting of three cascaded circuit blocks using 90 nm CMOS technology, an LNA [8], a mixer [9] and an output buffer [10]. The specifications of the three circuit blocks and the overall specifications of the front end are shown in Table I.…”

Section: Numerical Resultsmentioning

confidence: 99%

Power dissipation minimization in RF front ends

Baltus

Heuvel

et al. 2010

2010 IEEE 21st International Symposium on Personal, Indoor and Mobile Radio Communications Workshops

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Abstract-In mobile and portable wireless devices, it is important to have low power dissipation so as to maximize battery life. As the overall power dissipation of a device is dominated by the radio frequency (RF) front end rather than the digital circuit, low-power RF front end design has become a very hot topic in both research and implementation. In this paper, we propose a design method to minimize the power dissipation of a RF front end. Specifically, given the overall specifications of gain, linearity and noise figure of a front end, we derive the optimal specification for each building block of the RF front end such that the overall power dissipation is minimized. By using a specific example of a front end consisting of a couple of cascaded circuit blocks using 90nm CMOS technology, we demonstrate that significant reduction in power dissipation can be achieved using the proposed design method.

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Section: Numerical Resultsmentioning

confidence: 99%

Power dissipation minimization in RF front ends

Baltus

Heuvel

et al. 2010

2010 IEEE 21st International Symposium on Personal, Indoor and Mobile Radio Communications Workshops

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“…where the available receiver circuit power P r , satisfies P r = P min as in (13). This is achieved by expressing the power optimal IP 3 tot , called IP 3 tot , as a closed form function (21) of the figure of merits related to the used IC design process, the available receiver circuit power P r , the power optimal total noise factor F tot and total gain G tot .…”

Section: B Optimum Throughputmentioning

confidence: 99%

“…However, the throughput BT /P r expressed in bits/Joule cannot increase if a more power consuming circuit is used. Designing for better linearity than, to accommodate a crude modulation of 2.3 bit/s/Hz, does not pay off [12], and Output buffer [13] …”

Section: G Duty Cyclingmentioning

confidence: 99%

Optimal transmission rate for ultra low-power receivers

Heuvel

Linnartz

Baltus

2010

21st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications

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Abstract-In many wireless systems, the energy consumed by the receiver is significantly larger than the energy consumed by transmitter, possibly even by orders of magnitudes. This paper derives an analytical solution to maximize the throughput per unit of available receiver circuit power. Adaptive control of the IP3, to handle the time-varying adjacent channel interference level, can substantially improve the power efficiency, compared to the common practice of design for worst case. There appears to be an optimum throughput at a specific (non zero) power consumption level. For large SNR, the optimal throughput per Joule of receiver circuit power occurs for a modulation rate of 2.3 bits/s/Hz, irrespective of interference power level. If the receiver has less power available than the optimum setting requires, a duty cycling scheme can still achieve optimum operation.

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“…However, this broadband aspect makes the low-pow er design of the baseband section very challenging. The design of ultra-low power building blocks in advanced CMOS technologies is mandatory [3]- [4]. In this paper, the design of a baseband block merging Programmable Gain Amplifier function and filter function is presented.…”

Section: Introductionmentioning

confidence: 99%

A 240MHz programmable gain amplifier & filter for ultra low power low-rate UWB receivers

D'Amico

Basçhirotto

Philips

et al. 2009

2009 Proceedings of ESSCIRC

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A 90nm-CMOS power-optimized Programmable Gain Amplifier (PGA) for Ultra Low power Low Rate-Ultra Wide Band (LR-UWB) receivers is illustrated. The PGA features a 0-40dB programmable gain range with a 5dB gainstep. In addition it implements a 6 th -order 240MHz Bessel lowpass transfer function . The cut-off frequency is about constant, independently on the different gain settings. At 40dB gain, the input IdBcp is -44.8dBm, and the NF is 14.3dB. The current consumption (1.9mA at OdB-gain up to 2.9mA at 40dB-gain) is optimized by including the opamp performance in the cell transfer function , and accordingly to the selected gain level.

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A 90nm CMOS Variable-Gain Amplifier and RSSI Design for Wide-band Wireless Network Application

Cited by 19 publications

References 7 publications

Power dissipation minimization in RF front ends

Power dissipation minimization in RF front ends

Optimal transmission rate for ultra low-power receivers

A 240MHz programmable gain amplifier & filter for ultra low power low-rate UWB receivers

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A 90nm CMOS Variable-Gain Amplifier and RSSI Design for Wide-band Wireless Network Application

Cited by 19 publications

References 7 publications

Power dissipation minimization in RF front ends

Power dissipation minimization in RF front ends

Optimal transmission rate for ultra low-power receivers

A 240MHz programmable gain amplifier &#x00026; filter for ultra low power low-rate UWB receivers

Contact Info

Product

Resources

About

A 240MHz programmable gain amplifier & filter for ultra low power low-rate UWB receivers