A 90nm data flow processor demonstrating fine grained DVS for energy efficient operation from 0.25V to 1.2V

Shakhsheer, Yousef; Khanna, Sudhanshu; Craig, Kyle; Arrabi, Saad; Lach, John; Calhoun, Benton H.

doi:10.1109/cicc.2011.6055335

Cited by 16 publications

(20 citation statements)

References 9 publications

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“…DVS during active mode saves power by lowering the frequency and voltage together when timing slack exists. Applying DVS to multiple blocks requires multiple DC-DC converters that adjust the local voltage levels or alternative schemes that allow local V DD selection from among multiple regulated supplies [1]. Again, the overhead of these approaches can be substantial.…”

Section: Introductionmentioning

confidence: 98%

A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs

Craig

Shakhsheer

Khanna

et al. 2012

Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design

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This paper explores the benefits of splitting a monolithic power gate transistor into parallel, independently controlled, variable weighted power gates to provide programmable post-fabrication power grid resistance. This power gate topology creates energy saving opportunities by providing adjustable localized voltages during active modes and reducing leakage current in idle blocks while retaining data. Measurements show over 30% active energy savings per operation and 90% savings in idle current with retention. A modeling flow for a resistive power grid was also developed that demonstrates the effectiveness of this approach in a Bulldozer processor core.

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Section: Introductionmentioning

confidence: 98%

A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs

Craig

Shakhsheer

Khanna

et al. 2012

Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design

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“…On the vertical integration front, we wanted to know how the header transistors' sizes and the voltages of the rail can affect the system scheduler and whether the energy consumed in those headers during the 1 The graph has been taken from [4] V…”

Section: Research Questionsmentioning

confidence: 99%

Maximizing Energy Efficiency through Vertically Integrated Dynamic Reconfigurability

Arrabi¹

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Power and energy consumption have become some of the main hurdles for performance advancement in modern digital systems. High transistor densities and clock speeds have created significant thermal and power delivery issues, and increasingly pervasive portable electronic devices have limited energy sources but high performance expectations. Power affects and is affected by almost every aspect of digital system design, enticing designers and researchers to approach this problem from every possible aspect.This work explores two such aspects: dynamic reconfigurability and vertical integration. Dynamic reconfigurability is the ability to change the configuration of the system dynamically during runtime, and vertical integration is using low-level design information in high-level decisions (and vice-versa) as well as co-optimizing multiple design levels simultaneously. Both of these concepts can be targeted to various system metrics; in this work, they are used to reduce the total energy consumption of the system with the goal of increasing system battery lifetime while still providing the necessary performance and functional capabilities.This work explores dynamic reconfigurability and vertical integration through the use of three practical systems. We go through the steps and analysis in designing these systems that will show the potential benefits of our methods. Through the steps of designing the systems, we show the impact of several significant aspects of vertically integrated dynamically configurable systems, thus providing a framework for identifying potential benefits of reconfigurability and co-optimization and for general guidelines of how to implement them on other systems. We also look at the granularity of configurability and the overhead that it incurs, as well as the circuit-level details and information that might affect and be affected by architectural or system-level decisions.The first system is a wireless body sensor node that consumes most of its energy wirelessly transmitting data. We investigate how adaptive software can compress the data before sending without sacrificing information using only the limited processing and memory resources that typically reside on body sensors. We go through the various aspects that affect our solution and the different design levels we have to take into account when applying the compression.The second example system is a custom digital signal-processing system utilizing Panoptic Dynamic Voltage Scaling (PDVS), in which we investigate adding fine-grained spatial and temporal granularities of voltage scaling to the processor. We use a vertically integrated approach to explore the trade-offs of the ability to switch the voltage of a single arithmetic component (spatial) for a single operation (temporal), as well as the different variables that need to be considered for scheduling such systems.The third system is a Field Programmable Core Array (FPCA), in which we investigate various methods for creating a configurable processor capable of switching betwee...

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“…. over time; power waveform shows dithering between two rates to achieve an intermediate rate, resulting in near optimal average energy savings [10]. .…”

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confidence: 99%

“…97 5.9 a-c. Measured energy benefit (including overhead) of PDVS & MV DD vs. SV DD for single function single rate (SFSR) & single function multi rate (SFMR) at 67% and 50% at constant area d. Area benefit of PDVS over MV DD [10]. .…”

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confidence: 99%

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Lifetime Improvement in Body Sensor Networks

Shakhsheer

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Body sensor networks (BSNs) promise to provide significant benefits to the healthcare domain.BSNs consist of multiple nodes that sense, process, and transmit health data and an aggregator that manages nodes, processes data, and passes information between the nodes and the base station. Though BSNs have tremendous potential for improving health care, their practical adoption must overcome technical and social challenges such as form factor, battery life, and reliability. BSN nodes will not be adopted if they are unsightly, large and bulky, or require frequent battery changes or charging. The focus of this work is to improve BSN node and aggregator lifetime to improve the overall BSN lifetime. Improved BSN lifetime will augment remote, long-term monitoring of chronically-ill patients, firefighters, and athletes.The most desirable BSN lifetime is an infinite device lifetime; battery power constrains the lifetime of the device to a finite period of time. Energy harvesting mechanisms such as solar power, thermoelectric generation, and piezoelectric provide an alternative power source to these energy constrained devices for the possibility of infinite device lifetime. For a desired BSN node form factor of less than 1cm 3 , energy harvesting mechanisms can produce 50-100µWs. With careful design and tight system integration, BSN nodes can achieve this power consumption and potentially achieve an indefinite lifetime. This work presents the first wireless biosignal acquisition chip powered solely from a thermoelectric harvester and/or RF power with integrated supply regulation, analog front end, power management, subthreshold digital signal processing, and a transmitter. This work also investigates BSN architecture decisions such as tradeoffs between custom controllers and generic microcontrollers, to inform i ii future designs. Additionally, this work demonstrates the first-implemented on-chip, closedloop power management system capable of adjusting node power consumption to the amount of energy harvested and explores the power management design space.Aggregators cannot operate exclusively from energy harvesting due to their high processing/communication requirements and the inability to harvest a sufficient amount of energy.Therefore, the aggregator has become the determining factor in the BSNs lifetime. To extend lifetime of the aggregator and the whole BSN, we can leverage the aggregator's variable workload to improve battery lifetime by applying a fine-grained dynamic voltage scaling (DVS) scheme; this workload changes with amount of data that needs to be processed and the number of nodes with which are being communicated. This method, called Panoptic ("all-inclusive") Dynamic Voltage Scaling (PDVS), extends DVS to a finer granularity in space and time, allowing for much more flexible and energy efficient design and therefore a longer battery lifetime for the aggregator and a longer lifetime for the system. This work applies PDVS to a DSP data-flow processor as a proof of concept to show energy savings over m...

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A 90nm data flow processor demonstrating fine grained DVS for energy efficient operation from 0.25V to 1.2V

Cited by 16 publications

References 9 publications

A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs

A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs

Maximizing Energy Efficiency through Vertically Integrated Dynamic Reconfigurability

Lifetime Improvement in Body Sensor Networks

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