A 90nm RFID tag's baseband processor with novel PIE decoder and uplink clock generator

Shi, Weiwei; Choy, Chiu-Sing; Guo, Jianping; Chan, Chi Fat; Leung, Ka Nang; Pun, Kong Pang

doi:10.1109/mwscas.2010.5548910

Cited by 11 publications

(6 citation statements)

References 6 publications

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“…In subsequent stages of rectifier or multiplier, RFID digital core dissipates the most amount of power at one time restricting tag distance because activity of demodulator, backscatter modulator and standard functionalities on digital core are distributed over time. By using ultra low power design techniques, a RFID processor at 0.33 V supply voltage and 1 MHz input clock with 80 nW power consumption has been designed [13].…”

Section: Link Budget and Constituent Partsmentioning

confidence: 99%

Passive RFID Uplink and Downlink Link Budget and Comparison of ASK and BPSK Backscatter Modulations

Evecan

2019

Sakarya University Journal of Science

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Reflected signal levels in passive RFID require seperate TX and RX antennas to overcome the reader threshold. Using latest improvements, it is shown in this work that both the forward and backward links restrict communication distance given with equations depending upon tag power dissipation, antennas in use, type of modulation and operating environment and parameters to make both distances equal are given. Complete link budget for the forward and backward links in a RFID system are given with constituent parts in detail. After that, to further elaborate on the link budgets, reflection coefficient and power equations are obtained from a RFID front-end model with circuit theory and shown on a passive RFID system. This study shows modulation index m and antenna gain G t for BPSK and ASK modulations to make two distances equal for the environment to be within, found from two way link equations. Also, ASK and BPSK modulations are compared on communication distance for given average backscatter difference power, minimum SNR to targeted BER on the reader by the equations obtained on the circuit model and MATLAB simulations.

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Section: Link Budget and Constituent Partsmentioning

confidence: 99%

Passive RFID Uplink and Downlink Link Budget and Comparison of ASK and BPSK Backscatter Modulations

Evecan

2019

Sakarya University Journal of Science

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“…With elaborated configuration, the ACRL circuit can result in 1.4X~3X logic propagating speed when compared to the static CMOS cell designs. By applying ACRL cells in the proposed PIE decoder design, the decoder exhibits better performance than the similar standard-cell based one [6] in measurement. In conclusion, it is a valuable subthreshold design reference for passive RF transponders' baseband circuit design based on super-deep and deep submicron CMOS technologies.…”

Section: B Custom Acrl Cells For Pie Decodermentioning

confidence: 99%

Subthreshold passive RF tag's PIE decoder design with wide tolerance and custom ratioed logic cells

Shi

Choy

2014

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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A subthreshold PIE decoder design with wide tolerance for passive RF devices is presented. For the consideration of low power and low-voltage supply, energyaware structure with mixed counter and pre-counted addition are proposed. They also greatly reduces the impact of frequency variation. An innovative logic style is also proposed to achieve faster logic propagation in critical paths. It is an optimization from previous ratioed logics with pull-up current control and modified branches tailored to very-low supply voltage. The subthreshold active power can be suppressed to a comparable magnitude of static CMOS leakage. Fabricated in 90nm CMOS technology, the proposed PIE decoder can operate at 0.26~0.8 V with working clock frequency of equivalently 1.28~4.1 MHz, enhancing the overall robustness of the RF transponders.

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“…By applying the double-edge-triggered filp flop (DET DFF) in the Clock Tick Counter, the centered frequency of the clock from the ring oscillator can be equivalently halved to around 1.28 MHz [7]. In this way, the PVT variation is now greatly reduced and the frequency can be kept above 0.96 MHz (half of 1.92 MHz), extending the range of tolerance [7].…”

Section: B Subthreshold Data Link Portion For Wide Tolerancementioning

confidence: 99%

“…For the purpose of removing carry propagation, Galoi linear feedback shift register (LFSR) is utilized in the link frequency clock generator as a counter. The merit of LFSR is that the long carry propagation delay is replaced by simple XOR gate [7].…”

Section: B Subthreshold Data Link Portion For Wide Tolerancementioning

confidence: 99%

Subthreshold passive RFID tag's baseband processor core design with custom modules and cells

Shi

Choy

2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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Subthreshold ultra-low-power passive RFID tag's baseband processor core design with custom logic cells is presented in this paper, based on EPC C1G2 protocol. To deal with the critical timing and wide-range-PVT variation problems of the processor at very low power supply, and for the consideration of limited availability of RF power, power-aware ideas are applied to the processor, including data link portions. Importantly, a novel custom ratioed logic style is adopted in key modules to fundamentally solve the speed problem at ultra-lowvoltage. The proposed baseband processor was fabricated in 90nm CMOS as well as the regular design with the same function. In measurement the proposed design indicates good robustness and much more competent for subthreshold operation. It can operate at minimum 0.28V supply with power consumption of 129 nW.I.

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A 90nm RFID tag's baseband processor with novel PIE decoder and uplink clock generator

Cited by 11 publications

References 6 publications

Passive RFID Uplink and Downlink Link Budget and Comparison of ASK and BPSK Backscatter Modulations

Passive RFID Uplink and Downlink Link Budget and Comparison of ASK and BPSK Backscatter Modulations

Subthreshold passive RF tag's PIE decoder design with wide tolerance and custom ratioed logic cells

Subthreshold passive RFID tag's baseband processor core design with custom modules and cells

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