A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient AES Accelerator in 28nm CMOS

Shan, Weiwei; Fan, Ao; Xu, Jiaming; Seok, Mingoo

doi:10.23919/vlsic.2019.8778189

Cited by 6 publications

(1 citation statement)

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“…The area and power consumption of TPU-v1 is 331 mm 2 and 75 W, respectively. An ASIC low-power AES engine [40] achieves a 991 Mbps throughput at 875 MHz in 28 nm. The area and power consumption of the AES engine is 0.0031 mm 2 and 3.85 mW, respectively.…”

Section: Asic Area Overhead Estimatementioning

confidence: 99%

GuardNN: Secure Accelerator Architecture for Privacy-Preserving Deep Learning

Hua¹,

Umar²,

Zhang³

et al. 2020

Preprint

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This paper proposes GuardNN, a secure deep neural network (DNN) accelerator, which provides strong hardwarebased protection for user data and model parameters even in an untrusted environment. GuardNN shows that the architecture and protection can be customized for a specific application to provide strong confidentiality and integrity protection with negligible overhead. The design of the GuardNN instruction set reduces the TCB to just the accelerator and enables confidentiality protection without the overhead of integrity protection. GuardNN also introduces a new application-specific memory protection scheme to minimize the overhead of memory encryption and integrity verification. The scheme shows that most of the offchip meta-data in today's state-of-the-art memory protection can be removed by exploiting the known memory access patterns of a DNN accelerator. GuardNN is implemented as an FPGA prototype, which demonstrates effective protection with less than 2% performance overhead for inference over a variety of modern DNN models.

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Section: Asic Area Overhead Estimatementioning

confidence: 99%

GuardNN: Secure Accelerator Architecture for Privacy-Preserving Deep Learning

Hua¹,

Umar²,

Zhang³

et al. 2020

Preprint

View full text Add to dashboard Cite

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Embedding security into ferroelectric FET array via in situ memory operation

Xu,

Xiao,

Zhao

et al. 2023

Nat Commun

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Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable. Existing solutions to address the security issues of NVMs are mainly based on Advanced Encryption Standard (AES), which incurs significant performance and power overhead. In this paper, we propose a lightweight memory encryption/decryption scheme by exploiting in-situ memory operations with negligible overhead. To validate the feasibility of the encryption/decryption scheme, device-level and array-level experiments are performed using ferroelectric field effect transistor (FeFET) as an example NVM without loss of generality. Besides, a comprehensive evaluation is performed on a 128 × 128 FeFET AND-type memory array in terms of area, latency, power and throughput. Compared with the AES-based scheme, our scheme shows ~22.6×/~14.1× increase in encryption/decryption throughput with negligible power penalty. Furthermore, we evaluate the performance of our scheme over the AES-based scheme when deploying different neural network workloads. Our scheme yields significant latency reduction by 90% on average for encryption and decryption processes.

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