A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18&amp;#181;m Digital CMOS

Andersen, T.N.; Briskemyr, A.; Telsto, F.; Bjornsen, J.; Bonnerud, T.E.; Hernes, B.; Moldsvor, O.

doi:10.1109/date.2005.3

Cited by 5 publications

(4 citation statements)

References 6 publications

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“…Before turning to our numerical experiments, we briefly outline our implementation (Andersen, 2018). The code is written in Python and performs the following steps:…”

Section: Methodsmentioning

confidence: 99%

On the robustness and scalability of semidefinite relaxation for optimal power flow problems

Eltved

Dahl²,

Andersen

2019

Optim Eng

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Semidefinite relaxation techniques have shown great promise for nonconvex optimal power flow problems. However, a number of independent numerical experiments have led to concerns about scalability and robustness of existing SDP solvers. To address these concerns, we investigate some numerical aspects of the problem and compare different state-of-the-art solvers. Our results demonstrate that semidefinite relaxations of large problem instances with on the order of 10,000 buses can be solved reliably and to reasonable accuracy within minutes. Furthermore, the semidefinite relaxation of a test case with 25,000 buses can be solved reliably within half an hour; the largest test case with 82,000 buses is solved within eight hours. We also compare the lower bound obtained via semidefinite relaxation to locally optimal solutions obtained with nonlinear optimization methods and calculate the optimality gap.

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“…Before turning to our numerical experiments, we briefly outline our implementation (Andersen, 2018). The code is written in Python and performs the following steps:…”

Section: Methodsmentioning

confidence: 99%

On the robustness and scalability of semidefinite relaxation for optimal power flow problems

Eltved

Dahl²,

Andersen

2019

Optim Eng

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“…It is often implemented using a parser like CVX [20] and YALMIP [21] that converts mathematical expressions into a compatible data format for the solver, but this process is very slow, and usually destroys the inherent structure in the problem. Solver-specific implementations of clique tree conversion like SparseColo [22,23] and OPFSDR [24] are much faster while also preserving the structure of the problem for the solver. Nevertheless, the off-the-shelf solver is itself structure-agnotistic, so an improved complexity figure cannot be guaranteed.…”

Section: Comparisons To Prior Workmentioning

confidence: 99%

“…Define H and q according to (24). Then, under Assumption 1: (ii) We partition H into [H i,j ] i,j=1 to reveal a block sparsity pattern that coincides with the adjacency matrix of T : Incorporating the block topological permutation of Lemma 5 within any offthe-self interior-point method yields a fast interior-point method with overall time complexity of O(n 1.5 log(1/ )).…”

Section: Dualized Clique Tree Conversionmentioning

confidence: 99%

Sparse Semidefinite Programs with Near-Linear Time Complexity

Zhang

Lavaei

2018

2018 IEEE Conference on Decision and Control (CDC)

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Clique tree conversion solves large-scale semidefinite programs by splitting an n × n matrix variable into up to n smaller matrix variables, each representing a principal submatrix. Its fundamental weakness is the need to introduce overlap constraints that enforce agreement between different matrix variables, because these can result in dense coupling. In this paper, we show that by dualizing the clique tree conversion, the coupling due to the overlap constraints is guaranteed to be sparse over dense blocks, with a block sparsity pattern that coincides with the adjacency matrix of a tree. In two classes of semidefinite programs with favorable sparsity patterns that encompass the MAXCUT and MAX k-CUT relaxations, the Lovasz Theta problem, and the AC optimal power flow relaxation, we prove that the per-iteration cost of an interior-point method is linear O(n) time and memory, so an -accurate and -feasible iterate is obtained after O( √ n log(1/ )) iterations in near-linear O(n 1.5 log(1/ )) time. We confirm our theoretical insights with numerical results on semidefinite programs as large as n = 13659.

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“…In recent years pipeline ADC architecture becomes more attractive to achieve these SFDR requirements for high sampling rates with a standard CMOS process due to its insensitivity to offsets in comparators and operational amplifiers by using redundancy and digital correction [3,18,20]. Operational amplifier sharing technique is used to achieve low-power consumption and lowarea requirements [15].…”

Section: Introductionmentioning

confidence: 99%

A 94-mW, 100-MS/s, 12-bit pipeline ADC for multi-standard TV demodulation applications

Garcia-Gonzalez¹,

Greitschus²,

Desel³

2009

Analog Integr Circ Sig Process

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This paper presents the design and implementation of a 12-bit Analog-to-Digital Converter (ADC) for multi-standard TV demodulation applications. The ADC was fabricated in a standard digital 90-nm CMOS process and it is built by means of a front-end sample-and-hold and a cascade of 10 pipeline stages with 1.5-bits resolution. Performance of 60-dB signal-to-noise-ratio and 68-dB spurious-free-dynamic-range is obtained without calibration at 100-MS/s with a 1-V P-P input signal swing. The occupied silicon area is 0.5-mm 2 ; and the power consumption of 94-mW from a 1.2-V supply.

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A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18µm Digital CMOS

Cited by 5 publications

References 6 publications

On the robustness and scalability of semidefinite relaxation for optimal power flow problems

On the robustness and scalability of semidefinite relaxation for optimal power flow problems

Sparse Semidefinite Programs with Near-Linear Time Complexity

A 94-mW, 100-MS/s, 12-bit pipeline ADC for multi-standard TV demodulation applications

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