A 97mW 110MS/s 12b pipeline ADC implemented in 0.18μm digital CMOS

Andersen, T.N.; Briskemyr, A.; Telsto, F.; Bjornsen, J.; Bonnerud, T.E.; Hernes, B.; Moldsvor, O.

doi:10.1109/esscir.2004.1356664

Cited by 8 publications

(1 citation statement)

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“…It is worth noting that the FOM of the ADC in Ref. [11] is calculated from its analog power consumption, but not the total power consumption. In addition, compared with the ADCs OE12 14 with an LMS-based calibration technique, this ADC converts analog input to accurate digital output directly, instead of waiting for a convergence time.…”

Section: Measurement Resultsmentioning

confidence: 99%

A 12 bit 100 MS/s pipelined analog to digital converter without calibration

X¹,

Li²,

Zhang³

et al. 2010

J. Semicond.

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A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter (ADC) in a 0.18 m complementary metal-oxide semiconductor process is presented. The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements. A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation, respectively. With a 15.5 MHz input signal, the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s. The power consumption is 112 mW at a 1.8 V supply, including output drivers. The chip area is 3.51 mm 2 , including pads.

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Section: Measurement Resultsmentioning

confidence: 99%