A ΣΔ fractional- N synthesizer for GSM standard specifications

Abstract

We describe in this paper a new method for the characterization and optimization with heuristic algorithm of fractional-N synthesizer. This method will be applied to GSM application. The treated synthesizer based in the use a type-II third order Σ∆ modulator generates signals in 935-960 MHz range with 200 KHz resolution with a spur of less than -80 dBc/Hz. Optimal parameters values are so determined and verified by different simulations.

A frequency synthesizer with frequency divider and frequency multiplier for spur reduction

“…In conclusion, the advantages of the multiply-divide implementation are the phase noise performance, the switching speed, the high loop bandwidth, and the spurious performance. GSM standard requires that all spurious be 80dB below the carrier [69].…”