A Bandwidth Control Arbitration for SoC Interconnections Performing Applications with Task Dependencies

Ibarra-Delgado, Salvador; Sandoval-Arechiga, R.; Gómez-Rodríguez, José Ricardo; Ortiz-López, Manuel; Brox, Maria

doi:10.3390/mi11121063

Cited by 4 publications

(4 citation statements)

References 42 publications

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“…Ibarra-Delgado et al presented a fine-grained bandwidth control for on-chip interconnections configured in an SDNoC paradigm in [ 74 ]. The authors present the idea of a bandwidth control arbitration method for buses, switches, and routers.…”

Section: Literature Reviewmentioning

confidence: 99%

“…Buses: Dynamic reconfiguration buses with programmable priorities and arbitration policies to ensure bandwidth allocation [ 74 ], QoS, and resource reservation.…”

Section: Challenges and Opportunitiesmentioning

confidence: 99%

“…Moreover, a traffic regulator approach would help to characterize traffic before entering the network, for security and performance goals. -Buses: Dynamic reconfiguration buses with programmable priorities and arbitration policies to ensure bandwidth allocation [74], QoS, and resource reservation. These software components offer services aggregated as needed that complement the network operating system, such as secure protocols, network protocols, and configuration processes.…”

mentioning

confidence: 99%

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A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

et al. 2021

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Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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Section: Literature Reviewmentioning

confidence: 99%

“…Buses: Dynamic reconfiguration buses with programmable priorities and arbitration policies to ensure bandwidth allocation [ 74 ], QoS, and resource reservation.…”

Section: Challenges and Opportunitiesmentioning

confidence: 99%

mentioning

confidence: 99%

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A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

et al. 2021

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“…However, a significant hurdle is the escalating energy consumption during module communication, which imposes limitations on both application performance and architectural design. This escalating power consumption is emerging as a formidable challenge in contemporary SoC design [6].…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

Yadav,

Ahmed,

Ambudkar

et al. 2023

MMEP

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The rapid evolution of integration technology has significantly influenced System-on-Chip (SoC) design, characterized by the unprecedented integration of numerous functional modules onto ever-shrinking chips. Consequently, facilitating robust communication between these burgeoning modules has become critical to optimizing system functionality and performance. Traditional Bus architecture, however, proves inadequate in realizing this goal. To circumvent these communication impediments, mesh and torus interconnected architectures have been proposed, with cores interconnected within a single chip using diverse routing strategies for seamless operation. This study investigates a deterministic, deadlock-free routing protocol for a modified Fat-Tree topology that incorporates a core module at the intermediate level.Utilizing the Sniper simulator environment for evaluation, it is demonstrated that the proposed protocol surpasses the X-Y routing method used in both mesh and torus topologies in terms of power efficiency and throughput. The results show a 4%-8% reduction in power consumption compared to other approaches, indicating the superior efficacy of the proposed method.

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Efficient O-type mapping and routing of large-scale neural networks to torus-based ONoCs

Yao,

Meng,

Yang

et al. 2024

J. Opt. Commun. Netw.

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The rapid development of artificial intelligence has accelerated the arrival of the era of large models. Artificial-neural-network-based large models typically have millions to billions of parameters, and their training and reasoning processes put strict requirements on hardware, especially at the chip level, in terms of interconnection bandwidth, processing speed, latency, etc. The optical network-on-chip (ONoC) is a new interconnection technology that connects IP cores through a network of optical waveguides. Due to its incomparable advantages such as low loss, high throughput, and low delay, this communication mode has gradually become the key technology to improve the efficiency of large models. At present, the ONoC has been used to reduce the interconnection complexity of neural network accelerators, where neural network models are reshaped to map into the process elements of the ONoC and communicate at high speed on chip. In this paper, we first propose a torus-based O-type mapping strategy to realize efficient mapping of neuron groups to the chip. Additionally, an array congestion information-based low-congestion arbitrator is designed and then a multi-path low-congestion routing algorithm named TMLA is presented to alleviate array congestion and disperse the routing pressure of each path. Results demonstrate that the proposed mapping and routing scheme can reduce the average network delay without additional loss when the injection rate is relatively large, which provides a valuable reference for the research of neural network acceleration.

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A Bandwidth Control Arbitration for SoC Interconnections Performing Applications with Task Dependencies

Cited by 4 publications

References 42 publications

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

Efficient O-type mapping and routing of large-scale neural networks to torus-based ONoCs

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