A Bandwidth-Tracking Self-Biased 5-to-2800 MHz Low-Jitter Clock Generator in 55nm CMOS

Shu

2023

Preprint

A low-power wideband self-biased phase-locked loop (SPLL) is proposed for multi-protocol SerDes applications in this letter. With the proposed adaptive fast-locking current circuit (AFLCC), the settling time is reduced significantly, and no extra power and jitter contribution. In addition, a start-up module is adopted to reset the system to an optimal initial operating frequency quickly. The proposed 1-3-GHz SPLL, fabricated in TSMC 28-nm CMOS process and occupies a compact 0.028mm2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Only 0.96 mW is consumed from a 0.9 V supply at 1 GHz frequency.

“…Table I compares the proposed SPLL with the state-of-the-art PLLs [5][6][7][8][9]. The proposed SPLL improves the settling time at expenses of small area overhead.…”

Section: Start-up Loop and Circuitmentioning

confidence: 99%

A 0.9 V Wideband SPLL With an Adaptive Fast-Locking Circuit Achieving 24.68 μs Settling Time Reduction

Shu

2023

Preprint

“…A typical PLL tends to lock on the target state at a roughly constant speed due to the fixed bandwidth. The self-biased PLLs, which find the optimal operating bias level and charge pump (CP) current in an adaptive fashion [1,2], feature high stability, low jitter, and large operation range, and have been widely used [3][4][5][6]. Further, the self-biased PLLs are in no need of resistors and are independent of operating process, voltage, temperature (PVT) and frequency.…”

Section: Introductionmentioning

confidence: 99%

A 1-to-3 GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28 nm CMOS

Jia³

2022

Electronics

Based on a self-biased architecture, this paper presents a novel adaptive fast-locking, wide operating range and low-jitter phase-locked loop (PLL). A current injection and adaptive bandwidth technology with minimum area overhead is employed to speed up the loop equilibrium acquisition process, without any adverse impact on the steady-state loop dynamics and the jitter performance. The proposed start-up circuit resets the loop to an appropriate initial state in order to shorten the initial ramp-up interval of the voltage-controlled oscillator (VCO), also resulting in cutting down the pull-in time. In addition, a proportional factor is introduced to give some kind of flexibility in the circuit design optimization. The proposed adaptive fast-locking self-biased PLL (AFL-SPLL) is designed and realized in a prototype based on TSMC 28 nm CMOS process, having a supply voltage of 0.9 V and an area of 0.0281 mm2. This PLL demonstrates a tuning range of 1 to 3 GHz and power consumptions from 0.91 mW at 1 GHz to 4.6 mW at 3 GHz operating frequency. The experimental results show that the capture process has been accelerated by up to 84.7% over large division ratios, yet the capture performance did not deteriorate at all for small division ratios. Meanwhile, the circuit implementation gave almost no area increase and yet achieved a reduction in the lock-in time of about 6.5 times, namely from 23.5 μs (without the adaptive locking) to only 3.6 μs (with the adaptive locking) on the maximum operation frequency condition of 3 GHz.

A 0.9 V wideband SPLL with an adaptive fast‐locking circuit achieving 24.68 µs settling time reduction

Shu

2023

Electronics Letters

A low-power wideband self-biased phase-locked loop (SPLL) is proposed for multi-protocol SerDes applications in this letter. With the proposed adaptive fast-locking current circuit (AFLCC) and self-biased charge pump (CP), the settling time is reduced significantly, and no extra power and jitter contribution. In addition, a start-up module is adopted to reset the system to an optimal initial operating frequency quickly. The proposed 1-3-GHz SPLL, fabricated in TSMC 28-nm CMOS process, occupies a compact 0.028 mm 2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Only 0.96 mW is consumed at 1 GHz frequency.