2014 IEEE 12th Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) 2014
DOI: 10.1109/estimedia.2014.6962349
|View full text |Cite
|
Sign up to set email alerts
|

A Bayesian network approach for compiler auto-tuning for embedded processors

Abstract: The complexity and diversity of today's architectures require an additional effort from the programmers in porting and tuning the application code across different platforms. The problem is even more complex when considering that also the compiler requires some tuning, since standard optimization options have been customized for specific architectures or designed for the average case. This paper proposes a machine-learning approach for reducing the cost of the compiler auto-tuning phase and to speedup the appl… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
2
1

Citation Types

0
24
0
3

Year Published

2017
2017
2022
2022

Publication Types

Select...
3
3

Relationship

1
5

Authors

Journals

citations
Cited by 27 publications
(27 citation statements)
references
References 19 publications
0
24
0
3
Order By: Relevance
“…For application a i being optimized, n shows the number of optimizations under analysis [15]. The selection problem's optimization space has an exponential space as its upper-bound.…”
Section: 31mentioning
confidence: 99%
See 4 more Smart Citations
“…For application a i being optimized, n shows the number of optimizations under analysis [15]. The selection problem's optimization space has an exponential space as its upper-bound.…”
Section: 31mentioning
confidence: 99%
“…where n shows the number of optimizations under analysis [15,18]. However, the mentioned bound is a simpli ed phase-ordering problem having a xed length optimization sequence length and no repetitive application of optimizations.…”
Section: 31mentioning
confidence: 99%
See 3 more Smart Citations