A Bias‐Dependent Weight Update Characteristics of Low Power Synaptic Pass‐Transistors with a Hf‐Doped ZnO Channel Layer

Abstract

A study on a bias voltage‐dependent weight update characteristics in a sub‐threshold region of a low power synaptic pass‐transistor (SPT) is presented with a Hf‐doped zinc oxide active layer. The SPT is a synaptic thin‐film transistor (TFT) in series with a load TFT which is used as a resistive load (RL) to be scaled by a bias voltage (VB). Here, when the VB of the load TFT is modulated, the RL can be changed. With the changed RL, it is expected that the weight update characteristics (i.e., dynamic ratio) and electrical characteristics (i.e., power consumption) of the SPT are varied, respectively, suggesting a trade‐off relation between the dynamic ratio and power consumption. To check these, the pulsed characteristics of the fabricated SPT is monitored for different VB, respectively. From experimental results, as increasing VB, it is found that the decreased RL leads to the increase of the power consumption while enhancing the dynamic ratio because a full depression (FD) can be relatively easy. On the other hand, when the VB is reduced, the RL is increased resulting in the decrease of both the power dissipation and the dynamic ratio due to a difficulty of FD.