1992
DOI: 10.1109/82.127298
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A BiCMOS programmable frequency divider

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Cited by 9 publications
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“…1. An attempt to use BiCMOS to enhance the maximum clock frequency for a programmable divider was done in [ 2 ] . They reached a clock frequency of 165 MHz, still limiting the minimum dividing ratio to 8.…”
Section: Introductionmentioning
confidence: 99%
“…1. An attempt to use BiCMOS to enhance the maximum clock frequency for a programmable divider was done in [ 2 ] . They reached a clock frequency of 165 MHz, still limiting the minimum dividing ratio to 8.…”
Section: Introductionmentioning
confidence: 99%