A BIST and boundary-scan economics framework

Miranda, J.M.

doi:10.1109/54.605988

Cited by 12 publications

(3 citation statements)

References 2 publications

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“…One example was the use of weighting factors for the specific objectives [12]. Another way was the dedicated translation of all objectives into a single one, such as time-to-market to cost [13] or test escapes to cost [7].…”

Section: Multiobjective Optimization the Pareto Concept And Aumentioning

confidence: 99%

A "defect level versus cost" system tradeoff for electronics manufacturing

Scheffler

Franzon

Troster

2004

IEEE Trans. Electron. Packag. Manufact.

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Both cost and quality are important features when manufacturing today's high-performance electronics. Unfortunately, the two design goals (low) cost and (high) quality are somewhat mutually exclusive. High testing effort (and thus, quality) comes with a considerable cost, and lowering test activities has significant impact on the delivered quality. In this paper, we present a new structured search method to obtain the best combination of these two goals. It features a Petri-net oriented cost/quality modeling approach and uses a Pareto chart to visualize the results. The search for the Pareto-optimal points is done by means of a genetic algorithm. With our method, we optimize a manufacturing process for a global positioning system (GPS) front end. The optimized process clearly outperformed the standard fabrication process.Index Terms-Cost quality tradeoff, genetic algorithm, high-density packaging (HDP), Pareto chart.

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Section: Multiobjective Optimization the Pareto Concept And Aumentioning

confidence: 99%

A "defect level versus cost" system tradeoff for electronics manufacturing

Scheffler

Franzon

Troster

2004

IEEE Trans. Electron. Packag. Manufact.

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“…[1] compares DFT and non-DFT solutions at the IC level, especially in the areas of test cost and time to market. [8] gives a framework for analyzing the impact of BIST and boundary scan at the board and field levels. [11] describes a model for an assembly factory, and [5] discusses system test costs, but without considering the impact of DFT.…”

Section: Previous Workmentioning

confidence: 99%

Justifying DFT with a Hierarchical Top-Down Cost-Benefit Model

Davidson

2008

2008 IEEE International Test Conference

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How can we justify system level DFT? We must show that it has a positive return on investment (ROI). Existing test ROI models are manufacturing centric, do not account for the disaggregation of the product realization process, and are often focused on a specific DFT method. We propose a new, top-down, hierarchical ROI model, which starts with potential benefits and can handle entire systems more effectively than current models. IntroductionIt is well known that Design for Testability (DFT) improves quality and saves money. While DFT methods are now standard for most ICs, DFT at the system level is more problematic. One of the reasons for this is the lack of a full stream cost and benefit model, stretching from fab to field, that can help DFT proponents justify the addition of testability. There have been numerous models proposed at the IC level ( Wei [10], for instance) and models proposed at the system level, [11] but none with details on the costs and benefits at each stage of system design and integration, and none focused on the justification of DFT.The purpose of this paper is to provide such a model, but we will go about this in a slightly different way from previous efforts. These have labored to be precise and accurate. To do this, previous models are overly complex, and depend on parameters not known yet or difficult to obtain. Our model, on the other hand, has two goals:• Be detailed enough to give the DFT engineer advice on the important factors to be decided when making the decision to request DFT, and how much to propose. • Provide a convincing financial argument for the benefits of DFT. We don't believe that a manager deadset against DFT will be convinced by any model, but one in favor of it or leaning towards it will value a model to help convince upper management of the value of this effort. This means that the model must be kept simple and parameters which don't significantly affect the use/no-use decision should be dropped. There are some things considered in our model which we think have not been handled well in previous work:• Uncertainty. While Wei's model considers the uncertainty of both costs and benefits, this must be a fundamental part of any model. Understanding the benefits of DFT for an existing product and manufacturing process introduces far less uncertainty than trying to do so for a product yet to be built or designed.• The impact of disaggregation. DFT was first used by vertically integrated companies, where some additional expense at the IC level could benefit the companies bottom line at the system level. Today more systems are built from standard parts, and manufacturing has been outsourced. This limits the freedom of the DFT proponent to add DFT. • The impact of the distribution of actual field failures on the benefit analysis. While it is tough to make predictions, especially about the future, as Yogi Berra said, we want DFT to address the failures most likely to happen. Our model must take all of these factors into account. More importantly, the DFT advocate must take these...

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“…With the appropriate access features, the BIST can be reused at subsequent levels of product integration such as boards and systems. An economics framework of BIST and boundary scan has been carried out by various researchers (Miranda, 1997; Lu and Wu, 2000; Wei et al , 1997; Lin et al , 1998; Ungar and Ambler, 2001).…”

Section: Testingmentioning

confidence: 99%

VLSI interconnects and their testing: prospects and challenges ahead

Sharma¹,

Kaushik

Sharma

2011

Journal of Engineering, Design and Technology

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PurposeThe purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.Design/methodology/approachIn the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.FindingsThe effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.Originality/valueThis paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

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A BIST and boundary-scan economics framework

Cited by 12 publications

References 2 publications

A "defect level versus cost" system tradeoff for electronics manufacturing

A "defect level versus cost" system tradeoff for electronics manufacturing

Justifying DFT with a Hierarchical Top-Down Cost-Benefit Model

VLSI interconnects and their testing: prospects and challenges ahead

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