A BIST pattern generator design for near-perfect fault coverage

Chatterjee, Mitrajit; Pradhan, Dhiraj K.

doi:10.1109/tc.2003.1252851

Cited by 36 publications

(18 citation statements)

References 35 publications

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“…However, the method can be modified for a test-per-scan as well [3]. Multiplexers separating combinational parts of sequential circuits have to be present, similarly like in full-scan designs.…”

Section: Proposed Test Pattern Generator Design Methodsmentioning

confidence: 99%

“…The proposed column-catching method is compared with three state-of-the-art methods in this section, namely the bit-fixing accompanied by a "bit-correlating" ATPG [2], the "3-weight weighted random pattern BIST" proposed in [19] and the row matching method proposed in [3]. The comparison results are shown in Tab.…”

Section: Comparison With Other State-of-the-art Methodsmentioning

confidence: 99%

“…Let us mention here, that a special kind of a test pattern generator (GLFSR) is used in the row matching approach [3]. Using such a circuit causes quite a large area overhead in most cases, for many XOR gates involved.…”

Section: Comparison With Other State-of-the-art Methodsmentioning

confidence: 99%

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Column-matching based mixed-mode test pattern generator design technique for BIST

Fišer

Kubátová

2008

Microprocessors and Microsystems

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Section: Proposed Test Pattern Generator Design Methodsmentioning

confidence: 99%

Section: Comparison With Other State-of-the-art Methodsmentioning

confidence: 99%

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Column-matching based mixed-mode test pattern generator design technique for BIST

Fišer

Kubátová

2008

Microprocessors and Microsystems

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“…This is crucial to the quality component of testing. Chatterjee and Pradhan (2003) discussed that stored pattern BIST, requires high hardware overhead due to memory devices is in need to store pre computed test patterns, pseudorandom BIST, where test patterns are generated by pseudorandom pattern generators such as Linear Feedback Shift Registers (LFSRs) and Cellular Automata (CA), required very little hardware overhead. However, achieving high fault coverage for CUTs that contain many Random Pattern Resistant Faults (RPRFs) only with (pseudo) random patterns generated by an LFSR or CA often requires unacceptably long test sequences thereby resulting in prohibitively long test time.…”

Section: Introductionmentioning

confidence: 99%

Low Transition Test Pattern Generator Architecture for Built-in-Self-Test

Mohamed¹

2012

American Journal of Applied Sciences

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Problem statement:In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need long test time. Approach: This study presents a novel test pattern generation technique called Low-Transition Generalized Linear Feedback Shift Register (LT-GLFSR) with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. Intermediate patterns (by bipartite and bit (either 0 or 1) insertion technique) inserted in between consecutive test patterns generated by GLFSR which is enabled by a non overlapping clock scheme. This process is performed by finite state machine generate sequence of control signals. Low-Transition Generalized Linear Feedback Shift Registers (LT-GLFSR), are used in a circuit under test to reduce the average and peak power during transitions. LT-GLFSR patterns high degree of randomness and correlation between consecutive patterns. LT-GLFSR does not depend on circuit under test and hence it is used for both BIST and scan-based BIST architectures. Results and Conclusion: Simulation results prove that this technique has reduction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces the peak and average power consumption during test for ISCAS'89 bench mark circuits.

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“…Such an approach is exploited in the bit-fixing method [9,10], bit-flipping [11] and the method proposed in [12,13]. A similar principle is exploited in our column-matching method [14,15] as well.…”

Section: Introductionmentioning

confidence: 99%

Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST

Fišer

Kubátová

8th Euromicro Conference on Digital System Design (DSD'05)

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Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of faults should be detected by the pseudo-random phase, to reduce the number of faults to be covered in the deterministic one. We study the properties of different pseudo-random pattern generators. Their successfulness in fault covering strictly depends on the tested circuit. We examine properties of LFSRs and cellular automata. Four methods enhancing the pseudo-random fault coverage have been proposed. Then we propose a universal method to efficiently compute test weights.The observations are documented on some of the standard ISCAS benchmarks and the final BIST circuitry is synthesized using the Column-Matching method.

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A BIST pattern generator design for near-perfect fault coverage

Cited by 36 publications

References 35 publications

Column-matching based mixed-mode test pattern generator design technique for BIST

Column-matching based mixed-mode test pattern generator design technique for BIST

Low Transition Test Pattern Generator Architecture for Built-in-Self-Test

Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST

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