A bit-stream digital-to-analog converter with 18-b resolution

Kup, B.M.J.; Dijkmans, E.C.; Naus, P.J.A.; Sneep, J.

doi:10.1109/4.104166

Cited by 63 publications

(23 citation statements)

References 3 publications

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“…The noise shaping action performed by consecutive digital filtering can be then associated with the action of digital to analogue conversion [9,10,11] taking place at the output end of the digital audio system.…”

Section: Filtering the Shaped Noisementioning

confidence: 99%

“…For applications in instrumentation systems no further improvements can be obtained, but in digital audio systems where not the quantization error but the signal to noise ratio is of prime importance, further reduction of noise level can be obtained by including sophisticated digital filtering in digital-to-analogue converters [9][10][11].…”

Section: Time Domain Analysismentioning

confidence: 99%

See 1 more Smart Citation

Metrological Properties of a/D Converters Utilizing Higher Order Sigma–delta Modulators Compared With a/D Converters With Modulators of First Order

Sidor¹

2014

Metrology and Measurement Systems

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Time domain analysis is used to determine whether A/D converters that employ higher order sigma-delta modulators, widely used in digital acoustic systems, have superior performance over classical synchronous A/D converters with modulators of first order when taking into account their important metrological property which is the magnitude of the quantization error. It is shown that the quantization errors of delta-sigma A/D converters with higher order modulators are exactly on the same level as for converters with a first order modulator.

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Section: Filtering the Shaped Noisementioning

confidence: 99%

Section: Time Domain Analysismentioning

confidence: 99%

Metrological Properties of a/D Converters Utilizing Higher Order Sigma–delta Modulators Compared With a/D Converters With Modulators of First Order

Sidor¹

2014

Metrology and Measurement Systems

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“…The traditional CMOS static logic has proven to be inadequate for such applications, since it generates a considerable amount of power supply switching noise [5][6][7][8][9][10][11], due to the current spikes associated with switching gates. This supply noise couples with the analogue section via substrate coupling or power supply rails, leading to the degradation of resolution [8].…”

Section: Introductionmentioning

confidence: 99%

Modelling of source‐coupled logic gates

Alioto

Palumbo

Pennisi

2002

Circuit Theory & Apps

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SUMMARYIn this paper, the modelling of CMOS SCL gates is addressed. The topology both with and without output bu er is treated, and the noise margin as well as propagation delay performance are analytically derived, using standard BSIM3v3 model parameters.The propagation delay model of a single SCL gate is based on proper linearization of the circuit and the assumption of a single-pole behaviour. To generalize the results obtained to cascaded gates, the e ect of the input rise time and the loading e ect of an SCL gate are discussed.The expressions obtained are simple enough to be used for pencil-and-paper evaluations and are helpful from the early design phases, as they relate SCL gates performance to design and process parameters, allowing the designer to gain an intuitive understanding of performance dependence on design parameters and technology.The model has been validated by comparison with extensive simulations using a 0.35-m CMOS process. The model agrees well with the simulated results, since in realistic cases the di erence is less than 20% both for noise margin and delay. Therefore, the model proposed can be proÿtably used for pencil-and-paper evaluations and for computer-based timing analysis of complex SCL circuits.

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“…Although the layout design methods can reduce the effects of the digital switching noise, they are not sufficient for high-precision analog applications, and they require additional I/O pins and silicon area which increase the chip cost [2], [3].…”

Section: Introductionmentioning

confidence: 99%

A Wired-AND Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC

Ungan¹,

Askar²

1997

Analog Design Issues in Digital VLSI Circuits and Systems

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Abstract.A wired-AND current-mode logic (WCML) circuit technique in CMOS technology for low-voltage and high-speed VLSI circuits is proposed, and a WCML cell library is developed using standard 0.8 micron CMOS process. The proposed WCML technique applies the analog circuit design methodologies to the digital circuit design. The input and output logic signals are represented by current quantities. The supply current of the logic circuit is adjustable for the required logic speed and the switching noise level. The noise is reduced on the power supply lines and in the substrate by the current-steering technique and by the smooth swing of the reduced node potentials. Precise analog circuits and fast digital circuits can be integrated on the same silicon substrate by using the low noise property of the WCML. It is shown by the simulations that at low supply voltages, the WCML is faster and generates less switching noise when compared to the static-CMOS logic. At high speeds, the power dissipation of the WCML is less than that of the static-CMOS logic.

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A bit-stream digital-to-analog converter with 18-b resolution

Cited by 63 publications

References 3 publications

Metrological Properties of a/D Converters Utilizing Higher Order Sigma–delta Modulators Compared With a/D Converters With Modulators of First Order

Metrological Properties of a/D Converters Utilizing Higher Order Sigma–delta Modulators Compared With a/D Converters With Modulators of First Order

Modelling of source‐coupled logic gates

A Wired-AND Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC

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