A bitstream readback-based automatic functional test and diagnosis method for Xilinx FPGAs

Ruan, Anbang; Jie, Bairui; Wan, Li; Yang, Junhao; Xiang, Chuanyin; Zhu, Zujian; Wang, Yu

doi:10.1016/j.microrel.2014.03.017

Cited by 8 publications

(4 citation statements)

References 14 publications

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“…An FPGA consists of configurable logic blocks (CLBs), interconnect resources (IRs), and Input/output blocks (IOBs), each component consists of logic gates, D Flip-Flops (DFFs) and control units. FPGAs have increasingly plays an important role in modern electronic industry due to their features like reconfigurability, adaptability, less improvement cost, and diminished time-to-market [26]. FPGA is to be sure considerably more perplexing than basic show of Gates.…”

Section: Fpga Programmingmentioning

confidence: 99%

A Gracefully Degrading and Energy-Efﬁcient FPGA Programming using LabVIEW

Reddy

Suresh

Ramesh

2016

IJRES

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<p>Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.</p>

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Section: Fpga Programmingmentioning

confidence: 99%

A Gracefully Degrading and Energy-Efﬁcient FPGA Programming using LabVIEW

Reddy

Suresh

Ramesh

2016

IJRES

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show abstract

“…FPGA essentially consists of large array of gates which are programmable and can be reconfigured anytime anywhere. "Large array of gates" is an oversimplified description of FPGA [7]. FPGA is to be sure considerably more perplexing than basic show of Gates.…”

Section: Bmentioning

confidence: 99%

An efficient approach for design and testing of FPGA programming using Lab VIEW

Reddy

Suresh

Ramesh

et al. 2015

2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA's have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Veri log is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.

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“…It should be noted that fault diagnostic resolution is dependent on algorithms for FPGA test and diagnosis, whereas the algorithms are relevant to IOB numbers. The detail of the algorithms is introduced in our paper [15]. Instead of observing response values through I/O pins, our bitstream readback based FPGA test system employs DFFs in CLBs as monitoring points.…”

Section: ) Bitstream Parsing Modulementioning

confidence: 99%

“…The proposed FPGA testing system physically consists of software tools in a PC and an FPGA-under-test with the JTAG-to-USB cable in between. Except some available commercial EDA software tools, the other modules or software tools are developed based on the algorithms mentioned in paper [15].…”

Section: Evaluation Of the Proposed Test Systemmentioning

confidence: 99%

A bitstream readback based FPGA test and diagnosis system

Ruan

Jie

2014

2014 International Symposium on Integrated Circuits (ISIC)

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This paper presents a bitstream readback based automatic functional testing system for field-programmable gate array (FPGA) test and diagnosis. The proposed testing system physically consists of software tools in a PC and an FPGA-undertest with a communication channel in between. Hardware overhead is minimized due to no additional hardware required. Some software tools for boundary scan controlling, bitstream parsing as well as fault test and diagnosis are in-house developed. Leveraging the bitstream parsing tool, current states of D flipflops (DFFs) and configuration memory cell along with their absolute addresses can be obtained from readback bistreams and bitstream parsing library, respectively. Fault types and physical locations can be further determined by the fault test and diagnosis tool. The issue of IOB number limitations not addressed well by some previous work can be partly relieved along with reduced configuration numbers and improved diagnostic resolution. The BIST system is evaluated by testing several Xilinx series FPGAs, and experimental results are provided.

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A bitstream readback-based automatic functional test and diagnosis method for Xilinx FPGAs

Cited by 8 publications

References 14 publications

A Gracefully Degrading and Energy-Efﬁcient FPGA Programming using LabVIEW

A Gracefully Degrading and Energy-Efﬁcient FPGA Programming using LabVIEW

An efficient approach for design and testing of FPGA programming using Lab VIEW

A bitstream readback based FPGA test and diagnosis system

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