A bitstream reconfigurable FPGA implementation of the WSAT algorithm

Abstract

A field programmable gate array (FPGA) implementation of a coprocessor which uses the WSAT algorithm to solve Boolean satisfiability problems is presented. The input is a SAT problem description file from which a software program directly generates a problem-specific circuit design which can be downloaded to a Xilinx Virtex FPGA device and executed to find a solution. On an XCV300, problems of 50 variables and 170 clauses can be solved. Compared with previous approaches, it avoids the need for resynthesis, placement, and routing for different constraints. Our coprocessor is eminently suitable for embedded applications where energy, weight and real-time response are of concern.Abstract-Field programmable gate array (FPGA)-based systems provide advantages over conventional hardware including: 1) availability of the hardware during design and debug; 2) programmability; and 3) visibility. These three advantages can greatly shorten the design and verification cycle. This paper discusses a design environment that exploits these three FPGA-specific advantages to create a unified simulation/execution debug environment implemented in the JHDL design system. The described system provides a hardware debugging environment with the functionality of a simulator but up to 10 000 faster. In addition, testbenches and other typical verification software used in simulators can be used to verify running hardware.Index Terms-Debug, field programmable gate array (FPGA), reconfigurable computing.

An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA

“…Several approaches to accelerate simple WSAT algorithms by hardware systems have been proposed [9]- [11]. However, the size of the problems which can be solved by those hardware solvers are very limited.…”

Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor

“…The satisfiers implement variations of the classical full search Davis -Putnam (DP) SAT, algorithm [18]. More recently, incomplete, local search SAT algorithms like WSAT or GSAT have also been contemplated with configware implementations [14,19]. An interesting survey comparing the various approaches that have been proposed in the literature is given in [20].…”

“…The most important problems addressed by the various proposals are the following: (1) the method used to select the next decision variable and its value to be tried [8,16,17]; (2) the compilation time spent in preparing the FPGA -based circuit to be emulated [14,16,17]; (3) the ability to solve problems of an arbitrary large size [12,16,17]; software-hardware partitioning [13,14,16,17].…”

“…Several research groups have recently explored different approaches to implement SAT on configurable hardware [8][9][10][11][12][13][14][15][16][17], as an alternative to software SAT solvers. The satisfiers implement variations of the classical full search Davis -Putnam (DP) SAT, algorithm [18].…”

H-SIMD machine: configurable parallel computing for matrix multiplication

“…However, mapping an application algorithm to multimillion-gate FPGAs is time consuming, and may incur high configuration overhead and large configuration files [4]. The substantial communication and interrupt overheads between the workstation and the FPGAs also is a major performance bottleneck that may prevent further exploitation of the performance benefits gained from the parallel FPGA implementation [3].…”