A Blind Baud-Rate ADC-Based CDR

Abstract

ADC-based receivers process the received data in the digital domain, eliminating the need for much of the analog front end. In addition, a feed-forward blind architecture [1,2] eliminates the feedback loop between digital and analog domains so that the ADC and digital CDR can be designed and simulated independently. Previous works [1,2] sampled the incoming data at 2 samples per UI and at 1.45 samples per UI to achieve 5Gb/s and 6.875Gb/s, respectively. To further increase the data rate to 10Gb/s, we sample at baud rate (1 sample per UI). Existing baud-rate architectures [3] rely on a phase-tracking clock to sample at the middle of the data eye. This paper presents a blind baud-rate CDR, fabricated in 65nm CMOS. At 10Gb/s, the CDR demonstrates a high-frequency jitter tolerance of 0.19UI with ±300ppm of frequency offset. Also, the CDR demonstrates successful operation with 1000ppm offset, which amounts to sub-baud-rate sampling. Figure 7.4.1 illustrates the main challenge in the blind baud-rate sampling approach. Given an ideal channel, the data eye is open when sampled with a phase range spanning 1UI. However, with blind sampling, frequency offset between the data and receiver clock will cause the baud-rate sampling phase to shift continuously across a 1UI window. When the sampling occurs near the boundary, any high-frequency jitter may shift the sampling outside the 1UI phase range, resulting in the loss of data bits (i.e., zero jitter tolerance). To increase jitter tolerance, we introduce a controlled amount of ISI in the data by using a rectangular filter implemented as an integrate-and-dump (I&D) circuit [4] in the receiver front end. A 1UI rectangular filter, convolved with the ideal channel, spreads the pulse response to 2UI. If we have a perfect DFE to cancel all postcursor ISI, then the eye would be open for a range of 1.5UI. If the blind samples shift beyond the 1UI window, there is still a remaining jitter margin of 0.5UI pp . A 2UI rectangular filter increases this margin to 1UIpp and results in a symmetric eye opening with respect to the blind sampling window. For these reasons, we choose a 2UI I&D circuit in our design. The front end consists of four interleaved I&D and ADC blocks, each operating at 2.5GS/s. The I&D circuit integrates over 1UI intervals and samples the result, which the ADC converts into 5b digital values that are demuxed into 16 parallel samples. The digital CDR adds adjacent 5b 1UI I&D samples to synthesize 6b 2UI I&D samples. Since our ADC resolution is limited to 5 bits, if we were to obtain 2UI I&D samples directly in the analog domain and feed them to the ADC, we would have lost the added resolution.The digital CDR contains a feedback loop including a data interpolator, a speculative 2-tap DFE, a speculative Mueller-Muller phase detector (MMPD), and a conventional 2 nd -order loop filter. The data interpolator estimates the desired sample at the average interpolation phase (ϕ avg ) by linearly combining neighbouring blind samples. Given a negative frequency offset (i.e., data ...

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“…The first term in (8) is the expression of the standard normal distribution, so (9) According to the Taylor expansion formula, we can know that exp(-y 2 /2)≈1-y 2 /2, so the second term in (8) can be obtained as: (10) Substituting ( 9) and ( 10) into (8), we can get (11) Similarly, we can have (12) Substituting ( 11) and ( 12) into (6), we can get In the simulation, we use pseudo random bit sequence (PRBS) code to simulate the real data streams, and the transformation probability of the data is equal. In other words, the transition density KTD of MMPD is 0.5, which is the same as BBPD.…”

A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver

“…priate, or the signal quality is good as a square wave [9,10]. Liu et al [11] pro model for a Mueller-Muller CDR circuit and used a drift bit width to ch influence of the reference Vref level, which showed the phase drift that occu Vref was not set properly through simulations.…”

“…The convergence goal of traditional Mueller-Muller clock and data recovery (MM-CDR) circuits is to make the size of the pre-cursor equal to the size of the post-cursor, which requires a reference Vref level to generate the up/down signal. However, MM-CDR circuits face the problem of unstable convergence when the Vref matching is not appropriate, or the signal quality is good as a square wave [9,10]. Liu et al [11] proposed a linear model for a Mueller-Muller CDR circuit and used a drift bit width to characterize the influence of the reference Vref level, which showed the phase drift that occurred when the Vref was not set properly through simulations.…”

Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits

“…The rapid growth of data rate makes the classical Bang-Bang phase detector (BBPD) no longer suitable for high-speed clock and data recovery (CDR). However, the advantage of the Mueller-Muller phase detector (MMPD) that requires only one sample per symbol alleviates the problem of BBPD timing tension and exponential growth of power consumption in high-speed situations, making Mueller-Muller baud-rate sampling widely used in the serial IO design [2][3][4][5][6].…”