2005 IEEE International Symposium on Circuits and Systems
DOI: 10.1109/iscas.2005.1465865
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A BPSK Demodulator Circuit using an Anti-Parallel Synchronization Loop

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Cited by 2 publications
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“…There is 180° phase difference between the two phase-locked loops, and thus the name "anti-parallel" dual loop. In one of our previous works [8] we demonstrated a proto-type of this circuit using low-frequency (i. e., baseband) packaged components. In this paper, we describe the unique monolithic implementation of the circuit at a microwave carrier frequency of 2.7 GHz.…”
Section: Mmic Coherent Bpsk Demodulatormentioning
confidence: 99%
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“…There is 180° phase difference between the two phase-locked loops, and thus the name "anti-parallel" dual loop. In one of our previous works [8] we demonstrated a proto-type of this circuit using low-frequency (i. e., baseband) packaged components. In this paper, we describe the unique monolithic implementation of the circuit at a microwave carrier frequency of 2.7 GHz.…”
Section: Mmic Coherent Bpsk Demodulatormentioning
confidence: 99%
“…Generating these opposite signals requires a voltage difference between the two inputs to the comparator from the dual loop. As described in [8], two identical DC offset voltages V dc are introduced to the phase detectors (by using two voltage summers after the multipliers) to differentiate their two outputs. In this manner, when the locking loop is locked, its multiplier's output (IF) has to be -V dc , in order to cancel the introduced offset voltage V dc at the summer.…”
Section: Mmic Coherent Bpsk Demodulatormentioning
confidence: 99%