A buffer-space allocation approach for application-specific Network-on-Chip

A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs

“…In [33], a self-similar fractal-geometrybased triangle topology, called FracNoC is proposed for SoCs. In [34], another fractal topology that is the WK-recursive network is presented. Fractal based topologies have attractive properties, such as high degree of regularity, efficient communication performance for low energy consumption, and the ease of extendibility that suit NoC systems.…”

“…at application-level, at communication-level, or at physicallevel, as illustrated in Fig. 4 (e.g., [24,34,38,39,40]). At communication level, switching, network flow control, and data routing techniques should be carefully designed [43].…”

“…Fractal architectures are receiving considerable attention in networking community [9,27,32,33,34]. A fractal topology is defined as a geometric structure that demonstrates similarity in properties at various scales, i.e., the structure look similar under different magnification levels [32].…”

The network calculator for NoC buffer space evaluation

“…To show the effectiveness of this model, the analytical results were compared with those extracted from the simulation. However, deterministic approaches assume that the designer have a deep knowledge about the pattern of communication among cores and switches [3]. This leads to high computational complexity in implementation.…”

“…This group of methods is based on the use of analytical methods for calculation of NoC timing characteristics [1][2][3][4]. Present network calculators can be divided into the following groups: deterministic; physical; based on queuing system; probabilistic.…”