A built-in-self-test scheme for digital to analog converters

This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in segmented and binary weighted digital to analog converters (DACs). The BIST scheme comprises of a hierarchy of tests including tests for non-monotonicity, checks to detect if the DNL/INL errors exceed ±0.5 LSB and actual estimation of the DNL/INL. The BIST scheme has been experimentally verified on 10-bit segmented current steering DAC. The DAC, along with the additional circuits required for testing, was designed and fabricated using a 0.35 µm process. Both simulation and experimental results are included in this paper. Errors estimated using the BIST scheme match well with measurements done on the fabricated device.

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“…A VCO with much lower linearity can used by modulating the VCO with the step size rather than the DAC output voltage. This is proposed in [20].…”

Section: Comparison With Previous Schemesmentioning

confidence: 98%

A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs

Rafeeque

Vasudevan

2004

J Electron Test

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“…Analog fault detection is a pattern recognition task. Although, there are different fault detection methods, most of them can not be used for analog fault detection [2]. Computational intelligence embraces many approaches to pattern recognition resulted from the combination of techniques of different fields.…”

Section: Introductionmentioning

confidence: 99%

New Approach of Test for DAC Using Fuzzy Neural Networks

Masoumi

Mohammadi²

2007

Seventh International Conference on Intelligent Systems Design and Applications (ISDA 2007)

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Due to the existence of analogue signals, testing the mixed signal circuits is a complex and complicated one. D/A converters are one of the most important types of these circuits. In this paper, a method is presented to determine the points where faults are occurred in a 4-bit resistive ladder D/A converter, using fuzzy rules. For the purpose of implementing fuzzy rules, neural networks have been utilized. Also for improvement the fault coverage of this test method the LVQ neural network has been used. Firstly, the circuit has been simulated using ORCAD9 and then training patterns have been elicited. Continually, network simulation and training have been implemented via MATLAB6.1 TM .

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