A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

Cao, Xugang; Jiao, Hailong; Marinissen, Erik Jan

doi:10.1109/tcsii.2021.3096885

Cited by 9 publications

(4 citation statements)

References 13 publications

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“…They preserve the combinational logic state when the cell changes mode from functional to shift, which helps to reorder patterns effectively for minimizing power. Though the fanout of the scan port of the cell is usually one and so redundant toggle on it during functional mode results in minimal additional power, the cell presented in [10] blocks it saving the additional power during functional operation. Special scan cell which can be used to save power during shift operation presented in [14]- [17].…”

Section: Classificationmentioning

confidence: 99%

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Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

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Section: Classificationmentioning

confidence: 99%

“…Furthermore, the cell retains captured value after changing to shift mode, a valuable property for pattern reordering. Cao et al [10] presented a scan flip-flop with a data retention feature. It contains separate slave latches for functional and shifts purpose.…”

Section: Classificationmentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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“…Hence, new testing methods are developed to reduce the cost of overhead circuitry and testing time along with the boosting of fault coverage. Generally, the testing is done by applying a test vector to the circuit and comparing the results to the predicted results [7,8]. However, large test vectors are required to test a circuit when the feature sizes are decreased and device complexity is increased.…”

Section: Introductionmentioning

confidence: 99%

A Universal BIST Approach for Virtex-Ultrascale Architecture

Sathiabama¹,

Anila²

2023

Computer Systems Science and Engineering

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Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks . The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs' capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost.

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“…In the prior art there are two approaches to achieve a low leakage flip-flop (FF) with data retention capability 1) nonvolatile data retention FF (NV-FF) [1], [2], [3], [4], [5], [6], [7], [8], [9], [10] and 2) CMOS FF with a balloon latch (DR-FF). The NV-FF allows zero power consumption to maintain the data during the sleep mode, whereas the DR-FF requires an always-on circuity to preserve the data [11], [12], [13], [14], [15], [16]. Nevertheless, NV-FFs have several disadvantages over CMOS DR-FFs, particularly for duty-cycled systems with short and frequent sleep modes.…”

Section: Introductionmentioning

confidence: 99%

A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

Sedighiani

Singh

Jordans

et al. 2023

IEEE Trans. Circuits Syst. II

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A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

Cited by 9 publications

References 13 publications

Developments in scan shift power reduction: a survey

Developments in scan shift power reduction: a survey

A Universal BIST Approach for Virtex-Ultrascale Architecture

A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

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