A cache replacement policy to reduce cache miss rate for multiprocessor architecture

Lim, Ho Joon; Kim, Jaehwan; Chong, Jong‐Wha

doi:10.1587/elex.7.850

Cited by 3 publications

(4 citation statements)

References 4 publications

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“…This analysis will provide clues into classifying SVM kernels and number of features across particular memory access behaviors in the future. Across positive results for 6 features, SVM-predicted bypass yields an average miss rate decrease of 6.72%, which compared to related work such as [9] which achieves a 6.01% average, shows that SVM-predicted bypass can provide cache utilization comparable to ad hoc replacement policy mechanisms.…”

Section: Resultsmentioning

confidence: 70%

“…In [1], Kharbutli et al relaxed cache inclusion and bypassed data from L2 (LLC) only, requiring less hardware overhead. Similarly focused on LLC, [9] creates new replacement policy on last-level shared cache (L2) by adding two tables and counter. Later, Xiang et al [10] suggested that bypassing only never-reused lines is not enough; lines which are least reused should also be bypassed.…”

Section: Related Workmentioning

confidence: 99%

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Applying SVM to data bypass prediction in multi core last-level caches

Sritriratanarak

Ekpanyapong

Chongstitvatana

2015

IEICE Electron. Express

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Bypassing emerged as a performance improvement method for shared Last-Level Caches (LLC) in multicore processors where large data portions are never reused, wasting system resources. This paper proposes an alternative method to predict data bypassing using Support Vector Machine (SVM). Based on access traces obtained from a simulator, SVM is trained to generate bypass models which are integrated into the simulator to quantify LLC performance improvements. Results show that SVM can classify which data to bypass, improving LLC performance, achieving an average 6.72% miss rate decrease across SPLASH2 benchmark combinations.

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Section: Resultsmentioning

confidence: 70%

Section: Related Workmentioning

confidence: 99%

Applying SVM to data bypass prediction in multi core last-level caches

Sritriratanarak

Ekpanyapong

Chongstitvatana

2015

IEICE Electron. Express

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“…Some prioritize blocks based on their recency of access, such as LRU, SRRIP [14] and PDP [16]. Other use the frequency of accesses, like LFU, LFRU [17] and SAR [18]. The re-reference distance is the basis for Timekeeping [19], EHC [20] and Leeway [21].…”

Section: Replacement Policies For Shared Caches In Multicore Processorsmentioning

confidence: 99%

Near-optimal replacement policies for shared caches in multicore processors

et al. 2021

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An optimal replacement policy that minimizes the miss rate in a private cache was proposed several decades ago. It requires knowing the future access sequence the cache will receive. There is no equivalent for shared caches because replacement decisions alter this future sequence. We present a novel near-optimal policy for minimizing the miss rate in a shared cache that approaches the optimal execution iteratively. During each iteration, the future access sequence is reconstructed on every miss interleaving the future per-core sequences, taken from the previous iteration. This single sequence feeds a classical private-cache optimum replacement policy. Our evaluation on a shared last-level cache shows that our proposal iteratively converges to a near-optimal miss rate that is independent of the initial conditions, within a margin of 0.1%. The best state-of-the-art online policies achieve around 65% of the miss rate reduction obtained by our near-optimal proposal. In a shared cache, miss rate optimization does not imply the optimization of other metrics. Therefore, we also propose a new near-optimal policy to maximize fairness between cores. The best state-ofthe-art online policy achieves 60% of the improvement in fairness seen with our near-optimal policy. Our proposals are useful both for setting upper performance bounds and inspiring implementable mechanisms for shared caches.

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“…8 Mbytes) [7], utilizing last-level cache (LLC) is more flexible and promising. Prior LLC management schemes partition cache to isolate memory traffic with different characteristics and optimize resource allocation [8,9,10], or propose the optimal cache line replacement policy by accurately estimating reuse distance [11,12,13,14,15,16,17,18,19]. Some propose both partition and replacement scheme [20,21].…”

Section: Introductionmentioning

confidence: 99%

IP-aware cache partition and replacement scheme for mobile computing devices

Kim

Lee

2019

IEICE Electron. Express

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Mobile computing devices employ multiple task-specific IP cores to improve performance and energy. With the main memory shared by all CPU cores and IPs, it becomes a critical bottleneck as increasing multimedia IPs consume significant memory bandwidth whereas the improvement of memory bandwidth lags behind. We propose an IP-aware cache management scheme for the last-level cache to reduce the load on the main-memory, while satisfying QoS requirements of frame-based multimedia applications. Evaluation with CPU applications and 4 K/ 60 fps video streaming applications shows that our proposed scheme reduces DRAM bandwidth by 28.62% on average over LRU and completely avoids frame-drops.

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A cache replacement policy to reduce cache miss rate for multiprocessor architecture

Cited by 3 publications

References 4 publications

Applying SVM to data bypass prediction in multi core last-level caches

Applying SVM to data bypass prediction in multi core last-level caches

Near-optimal replacement policies for shared caches in multicore processors

IP-aware cache partition and replacement scheme for mobile computing devices

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