A Capacitively Coupled Chopper Instrumentation Amplifier With Compensated Auto-Zeroed DC Servo-Loop for Neural Signal Recording

Zhou, Zekun; Zhu, Longbin; Wang, Wenjie; Li, Jihong; Meng, Qiao; Wang, Zhigong

doi:10.1109/tcsii.2023.3291375

Cited by 4 publications

(2 citation statements)

References 19 publications

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“…where 𝜏 2 = 𝑅 𝑠𝑤,𝑜𝑛 𝐶 𝑖𝑛𝑡 (8) where Rsw,on is the on-resistance of SW1. During phase t4, the equivalent circuit is the same as the circuit at phase t2.…”

Section: Rpmentioning

confidence: 99%

“…The main loop is composed of two-stage amplifier (Gm1 and Gm2), input capacitors Cin and feedback capacitors Cf. PFL consists of a chopper and positive feedback capacitors Cpf, which is designed to boost the input impedance [7] [8]. Cpf connects the input with the output of CCIA and converts the output voltage into current that flows into Cin to reduce the input current.…”

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confidence: 99%

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A Capacitively Coupled Chopper Instrumentation Amplifier with Deadtime Offset Reduction Technique for Neural Signal Recording

Li¹,

Zhu²,

Su³

et al. 2023

Preprint

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This letter presents a deadtime offset reduction (DOR) technique to reduce the offset and ripple at the output of the capacitively coupled chopper instrumentation amplifier (CCIA) for neural signal recording. DOR employs switches to discharge the offsets at main amplifier and DC servo loop, during the deadtime of the chopping clocks. The circuits are targeted at IC realization and designed in 0.18-μm CMOS technology. The proposed CCIA with DOR achieves an output offset reduction ratio of 52 dB and a ripple reduction ratio of 47 dB without any significant increasement of power, area, or noise overhead.

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“…where 𝜏 2 = 𝑅 𝑠𝑤,𝑜𝑛 𝐶 𝑖𝑛𝑡 (8) where Rsw,on is the on-resistance of SW1. During phase t4, the equivalent circuit is the same as the circuit at phase t2.…”

Section: Rpmentioning

confidence: 99%

mentioning

confidence: 99%

A Capacitively Coupled Chopper Instrumentation Amplifier with Deadtime Offset Reduction Technique for Neural Signal Recording

Li¹,

Zhu²,

Su³

et al. 2023

Preprint

View full text Add to dashboard Cite

show abstract

A low noise CLASS AB operational amplifier with high voltage output capability by 180 nm BCD process

Li,

Luo,

Wei

2024

J. Phys.: Conf. Ser.

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In this work, a low noise CLASS AB operational amplifier, which can output high voltage, has been fabricated by a 180 nm BCD process. For the objective of achieving low noise, the bipolar junction transistor (BJT) input stage with the base current compensation structure is employed. Experimental results show that the low noise amplifier’s equivalent input current and voltage noise are 3.2 pA/sqrt (Hz) and 16.73 nV/sqrt (Hz) separately, and the rising and falling slew rates are 10.40 MV/s and 6.67 MV/s separately. With the die area of 0.629 mm2, the amplifier’s power consumption is 18.3 mW, which flows 60 μA on the 5 V low power supply and 600 μA on the 25 V high power supply.

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A Capacitively Coupled Chopper Instrumentation Amplifier With Deadtime Offset Reduction Technique for Neural Signal Sensing

Li,

Zhu,

et al. 2024

IEEE Sens. Lett.

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A Capacitively Coupled Chopper Instrumentation Amplifier With Compensated Auto-Zeroed DC Servo-Loop for Neural Signal Recording

Cited by 4 publications

References 19 publications

A Capacitively Coupled Chopper Instrumentation Amplifier with Deadtime Offset Reduction Technique for Neural Signal Recording

A Capacitively Coupled Chopper Instrumentation Amplifier with Deadtime Offset Reduction Technique for Neural Signal Recording

A low noise CLASS AB operational amplifier with high voltage output capability by 180 nm BCD process

A Capacitively Coupled Chopper Instrumentation Amplifier With Deadtime Offset Reduction Technique for Neural Signal Sensing

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