A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Wen, Xiaoqing; Miyase, Kohei; Kajihara, Seiji; Furukawa, Hiroshi; Yamato, Yuta; Takashima, Akira; Noda, K.; Ito, Hajime; Hatayama, Kazumi; Aikyo, Takashi; Saluja, Kewal K.

doi:10.1109/ets.2008.13

Cited by 32 publications

(12 citation statements)

References 10 publications

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“…The generated test set was regarded as the initial test set. In [10], the threshold value used to identify the capture-unsafe test vectors was set to 90% of the maximum capture-power metric values in the initial test set, and in [21], the threshold values were set to 15% and 20% of the theoretical maximum WSA values which was calculated when transitions occurred on all signal lines in a circuit. In this experiments, the threshold value used to identify the capture-unsafe test vectors was set to 70% of the maximum WSA values in the initial test set.…”

Section: Resultsmentioning

confidence: 99%

“…Methods based on circuit modification [6]- [9] attempt to reduce capture power by modifying the circuit structures or by inserting some additional hardware in the circuit under test (CUT). In contrast, methods based on test vector manipulation [10]- [22] generate capture-safe test vectors [10] that will not consume excessive power during testing.…”

Section: Introductionmentioning

confidence: 99%

“…Capture power values for LSA of capture-unsafe test vectors are more than the threshold value. Since capture-unsafe test vectors should not be used for at-speed low power scan testing, unsafe faults [10] which can only be detected by capture-unsafe test vectors remain undetected. It is important to reduce the number of unsafe faults to improve fault coverage.…”

Section: Introductionmentioning

confidence: 99%

“…Given a test set and a threshold value of capture power for LSA, test vectors are classified into capture-safe test vectors [10] and capture-unsafe test vectors [10]. Capture power values for LSA of capture-unsafe test vectors are more than the threshold value.…”

Section: Introductionmentioning

confidence: 99%

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A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation

Hosokawa

Hirai

Yamauchi

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYIn at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the response for a test vector is captured by flip-flops results in excessive voltage drops, known as IR-drops, which may cause significant capture-induced yield loss. In low capture power test generation, the test vectors that violate capture power constraints in an initial test set are defined as capture-unsafe test vectors, while faults that are detected solely by capture-unsafe test vectors are defined as unsafe faults. It is necessary to regenerate the test vectors used to detect unsafe faults in order to prevent unnecessary yield losses. In this paper, we propose a new low capture power test generation method based on fault simulation that uses capture-safe test vectors in an initial test set. Experimental results show that the use of this method reduces the number of unsafe faults by 94% while requiring just 18% more additional test vectors on average, and while requiring less test generation time compared with the conventional low capture power test generation method.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation

Hosokawa

Hirai

Yamauchi

et al. 2017

IEICE Trans. Inf. & Syst.

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“…These approaches to reduce switching activity in CUT include adding additional logic [3], scan architecture segmentation with gated clocking [4], scan cell redesigning [5], ordering of tests [6], modified test generation methods [7,8], and post-generation filling of unspecified values in test cubes [9,10].…”

Section: Introductionmentioning

confidence: 99%

Reducing Test Power and Improving Test Effectiveness for Logic BIST

Wang¹,

Cai²,

Xiang³

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

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Low‐Power Testing for Low‐Power LSI Circuits

Wen

Zorian

2012

Advanced Circuits for Emerging Technologies

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A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Cited by 32 publications

References 10 publications

A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation

A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation

Reducing Test Power and Improving Test Effectiveness for Logic BIST

Low‐Power Testing for Low‐Power LSI Circuits

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