A Case for a Flexible Scalar Unit in SIMT Architecture

Yang, Yi; Xiang, Ping; Mantor, Michael; Rubin, Norman; Hsu, Lin-Nei; Dong, Qunfeng; Zhou, Huiyang

doi:10.1109/ipdps.2014.21

“…Register compression is an orthogonal approach that tries to reduce power by exploiting the register value similarity property. Scalar unit [23,15,49] exploits a special case of value similarity where all thread registers of a warp register have the same value. Scalar register file [23] eliminates redundant power consumption in that case by storing the thread register value of only one SIMT lane shared across all lanes.…”

Section: Related Workmentioning

confidence: 99%

Warped-compression

Lee

¹

,

Kim

²

,

Koo

³

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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This paper presents Warped-Compression, a warp-level register compression scheme for reducing GPU power consumption. This work is motivated by the observation that the register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread registers is small. Removing data redundancy of register values through register compression reduces the effective register width, thereby enabling power reduction opportunities. GPU register files are huge as they are necessary to keep concurrent execution contexts and to enable fast context switching. As a result register file consumes a large fraction of the total GPU chip power. GPU design trends show that the register file size will continue to increase to enable even more thread level parallelism. To reduce register file data redundancy warped-compression uses low-cost and implementationefficient base-delta-immediate (BDI) compression scheme, that takes advantage of banked register file organization used in GPUs. Since threads within a warp write values with strong similarity, BDI can quickly compress and decompress by selecting either a single register, or one of the register banks, as the primary base and then computing delta values of all the other registers, or banks. Warped-compression can be used to reduce both dynamic and leakage power. By compressing register values, each warp-level register access activates fewer register banks, which leads to reduction in dynamic power. When fewer banks are used to store the register content, leakage power can be reduced by power gating the unused banks. Evaluation results show that register compression saves 25% of the total register file power consumption.

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“…Register compression is an orthogonal approach that tries to reduce power by exploiting the register value similarity property. Scalar unit [23,15,49] exploits a special case of value similarity where all thread registers of a warp register have the same value. Scalar register file [23] eliminates redundant power consumption in that case by storing the thread register value of only one SIMT lane shared across all lanes.…”

Section: Related Workmentioning

confidence: 99%

Warped-compression

Lee

¹

,

Kim

²

,

Koo

³

et al. 2015

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

This paper presents Warped-Compression, a warp-level register compression scheme for reducing GPU power consumption. This work is motivated by the observation that the register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread registers is small. Removing data redundancy of register values through register compression reduces the effective register width, thereby enabling power reduction opportunities. GPU register files are huge as they are necessary to keep concurrent execution contexts and to enable fast context switching. As a result register file consumes a large fraction of the total GPU chip power. GPU design trends show that the register file size will continue to increase to enable even more thread level parallelism. To reduce register file data redundancy warped-compression uses low-cost and implementationefficient base-delta-immediate (BDI) compression scheme, that takes advantage of banked register file organization used in GPUs. Since threads within a warp write values with strong similarity, BDI can quickly compress and decompress by selecting either a single register, or one of the register banks, as the primary base and then computing delta values of all the other registers, or banks. Warped-compression can be used to reduce both dynamic and leakage power. By compressing register values, each warp-level register access activates fewer register banks, which leads to reduction in dynamic power. When fewer banks are used to store the register content, leakage power can be reduced by power gating the unused banks. Evaluation results show that register compression saves 25% of the total register file power consumption. Bank ArbiterRegister Bank 0 Register Bank 31Operand Collector InterconnectRegister Bank 1

show abstract