A case for dynamic pipeline scaling

Koppanalil, Jinson; Ramrakhyani, Prakash; Desai, Sameer Feisal; Vaidyanathan, Anu; Rotenberg, Eric

doi:10.1145/581630.581632

Cited by 27 publications

(13 citation statements)

References 18 publications

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“…Alternatively, Shimada et al [1][2] and Koppanalil et al [3] presented a different method, which was expressed as pipeline stage unification (PSU) or dynamic pipeline scaling (DPS). Its main purpose is to reduce the processor's energy consumption via bypassing/inactivating part of pipeline registers and use shallow pipelines under a light workload.…”

Section: Baseline Technique and Related Workmentioning

confidence: 99%

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A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth

Miwa

Shimada

et al. 2011

J. Comput. Sci. Technol.

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Recently, a method known as pipeline stage unification (PSU) has been proposed to alleviate the increasing energy consumption problem in modern microprocessors. PSU achieves a high energy efficiency by employing a changeable pipeline depth and its working scheme is eligible for a fine control method. In this paper, we propose a dynamic method to study fine-grained program interval behaviors based on some easy-to-get runtime processor metrics. Using this method to determine the proper PSU configurations during the program execution, we are able to achieve an averaged 13.5% energydelay-product (EDP) reduction for SPEC CPU2000 integer benchmarks, compared to the baseline processor. This value is only 0.14% larger than the theoretically idealized controlling. Our hardware synthesis result indicates that the proposed method can largely decrease the hardware overhead in both area and delay costs, as compared to a previous program study method which is based on working set signatures.

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Section: Baseline Technique and Related Workmentioning

confidence: 99%

“…Pipeline stage unification (PSU) [1][2] and dynamic pipeline scaling (DPS) [3] are two specific ADP implementations. A detailed study indicated that a pipeline depth reconfiguration in PSU processors will only introduce a nanosecond-level switch penalty, which makes it eligible for a fine-grained energy optimization.…”

Section: Introductionmentioning

confidence: 99%

A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth

Miwa

Shimada

et al. 2011

J. Comput. Sci. Technol.

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“…Previous work has concentrated on hardware techniques, but how to solve this issue using software techniques remains open. For example, Koppanalil et al devised a DPS technique by switching the pipeline between deep mode and shallow mode at run time with respect to high and low frequencies, respectively [8]. Hiraki et al proposed a method that skipped several pipeline stages and then used a decoded buffer to replace the functionality of the original pipelines for low-power support [5].…”

Section: Related Workmentioning

confidence: 99%

“…However, DVS has no effect on energy saving when the voltage reaches its low bound because it becomes a constant [8]. Fortunately, with reference to (2), energy is in direct ratio not only to clock frequency and square of the voltage, but also to instruction-per-cycle (IPC).…”

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confidence: 99%

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Profile-based dynamic pipeline scaling

2008

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Low power has played an increasingly important role for embedded systems. To save power, lowering voltage and frequency is very straightforward and effective; therefore, dynamic voltage scaling (DVS) has become a prevalent lowpower technique. However, DVS makes no effect on power saving when the voltage reaches a lower bound. Fortunately, a technique called dynamic pipeline scaling (DPS) can overcome this limitation by switching pipeline modes at low-voltage level. Approaches proposed in previous work on DPS were based on hardware support. From viewpoint of compiler, little has been addressed on this issue. This paper presents a DPS optimization technique at compiler time to reduce power dissipation. The useful information of an application is exploited to devise an analytical model to assess the cost of enabling DPS mechanism. As a consequence, we can determine the switching timing between pipeline modes at compiler time without causing significant run-time overhead. The experimental result shows that our approach is effective in reducing energy consumption.

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