A case for globally shared-medium on-chip interconnect

Carpenter, Aaron; Hu, Jianyun; Xu, Jie; Huang, Michael C.

doi:10.1145/2000064.2000097

Cited by 26 publications

(6 citation statements)

References 50 publications

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“…low-latency barriers [26], [27], long-distance "express" links [28], [29] and connections between distant banks in large caches [30]. Shared-medium broadcast TL interconnects in [31] use optimizations to reduce on-chip traffic. While these optimizations defer the scalability problem, growth in core counts still inevitably leads to saturation of broadcast-type interconnects.…”

Section: B Related Workmentioning

confidence: 99%

Automatic OpenCL work-group size selection for multicore CPUs

Zajić

Prvulovic

2013

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques

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Growth in core count creates an increasing demand for interconnect bandwidth, driving a change from shared buses to packet-switched on-chip interconnects. However, this increases the latency between cores separated by many links and switches. In this paper, we show that a low-latency unswitched interconnect built with transmission lines can be synergistically used with a high-throughput switched interconnect. First, we design a broadcast ring as a chain of unidirectional transmission line structures with very low latency but limited throughput. Then, we create a new adaptive packet steering policy that judiciously uses the limited throughput of this ring by balancing expected latency benefit and ring utilization. Although the ring uses 1.3% of the on-chip metal area, our experimental results show that, in combination with our steering, it provides an execution time reduction of 12.4% over a mesh-only baseline.

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Section: B Related Workmentioning

confidence: 99%

Automatic OpenCL work-group size selection for multicore CPUs

Zajić

Prvulovic

2013

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques

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“…Instead, TLs are likely to be used strategically, e.g. to provide low-latency global connections for cache banks in very large caches [5], "express" long-distance network-on-chip (NoC) links [10,17], or as a chip-wide frequency-multiplexed bus [9].…”

Section: Background and Related Workmentioning

confidence: 99%

TLSync

Prvulovic

Zajić

2011

SIGARCH Comput. Archit. News

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As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament barrier, a larger number of cores results in a longer latency for each round and a larger number of rounds. Hardware barrier implementations require significant dedicated wiring, e.g., using a reduction (arrival) tree and a notification (release) tree, and multiple instances of this wiring are needed to support multiple barriers (e.g., when concurrently executing multiple parallel applications).This paper presents TLSync, a novel hardware barrier implementation that uses the high-frequency part of the spectrum in a transmission-line broadcast network, thus leaving the transmission line network free for non-modulated (baseband) data transmission. In contrast to other implementations of hardware barriers, TLSync allows multiple thread groups to each have its own barrier. This is accomplished by allocating different bands in the radio-frequency spectrum to different groups. Our circuit-level and electromagnetic models show that the worst-case latency for a TLSync barrier is 4ns to 10ns, depending on the size of the frequency band allocated to each group, and our cycle-accurate architectural simulations show that low-latency TLSync barriers provide significant performance and scalability benefits to barrier-intensive applications.

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“…To break these communication‐related scalability barriers of current multicore architectures, complementary interconnect technologies are currently being explored. On the one hand, these involve approaches based on guided waves such as nanophotonic networks [ 37 , 38 , 39 , 40 , 41 ] or radio‐frequency transmission lines [ 42 , 43 ] which benefit from energy efficiency and a large bandwidth; however, guided approaches intrinsically rely on physical infrastructure to connect the nodes which scales unfavorably because it requires increasingly stronger sources or more amplifiers, centralized arbitration, etc. On the other hand, WNoCs [ 44 , 45 ] avoid inter‐router hops and promise low‐latency broadcasting combined with intrinsic system‐level flexibility.…”

Section: Introductionmentioning

confidence: 99%

Metasurface‐Programmable Wireless Network‐On‐Chip

2022

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This paper introduces the concept of smart radio environments, currently intensely studied for wireless communication in metasurface‐programmable meter‐scaled environments (e.g., inside rooms), on the chip scale. Wireless networks‐on‐chips (WNoCs) are a candidate technology to improve inter‐core communication on chips but current proposals are plagued by a dilemma: either the received signal is weak, or it is significantly reverberated such that the on–off‐keying modulation speed must be throttled. Here, this vexing problem is overcome by endowing the wireless on‐chip environment with in situ programmability which enables the shaping of the channel impulse response (CIR); thereby, a pulse‐like CIR shape can be imposed despite strong multipath propagation and without entailing a reduced received signal strength. First, a programmable metasurface suitable for integration in the on‐chip environment (“on‐chip reconfigurable intelligent surface”) is designed and characterized. Second, its configuration is optimized to equalize selected wireless on‐chip channels “over the air.” Third, by conducting a rigorous communication analysis, the feasibility of significantly higher modulation speeds with shaped CIRs is evidenced. The results introduce a programmability paradigm to WNoCs which boosts their competitiveness as complementary on‐chip interconnect solution.

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A case for globally shared-medium on-chip interconnect

Cited by 26 publications

References 50 publications

Automatic OpenCL work-group size selection for multicore CPUs

Automatic OpenCL work-group size selection for multicore CPUs

TLSync

Metasurface‐Programmable Wireless Network‐On‐Chip

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