A case for hardened multiplexers in FPGAs

Abstract

Abstract-This paper presents a case for a hybrid configurable logic block that contains a mixture of LUTs and hardened multiplexers towards the goal of higher logic density and area reduction. Technology mapping optimizations, called MuxMap, that target the proposed architecture are implemented using a modified version of the mapper in the ABC logic synthesis tool. VPR is used to model the new hybrid configurable logic block and verify post place and route implementation. Multiple hybrid configurable logic block architectures with varying MUX:LUT ratios are evaluated across three benchmark suites with both Quartus II and Odin-II front-end RTL synthesis tools. Experimentally, we show that without any mapper optimizations we naturally save 4% area post place and route and with MuxMap optimizations in ABC yielding 6% area reduction post place and route while maintaining mapping depth, overall configurable logic block count, and routing demand.

Hybrid LUT/Multiplexer FPGA Logic Architectures

“…Sparse crossbars have been previously studied [19] and in this paper, we model a 50% depopulated crossbar within the CLB for intracluster routing for both nonfracturable and fracturable architectures as compared with the preliminary publication [15] that only modeled a full input crossbar. Extended discussion on architecture modelling follows in Section V.…”

“…Compared with the preliminary publication [15], we have also fully modeled all MUX inputs for wholly accurate MUX4 input mapping. Previously, all the MUX data-inputs were optimistically modeled to be equivalent and interchangeable.…”

“…Differing from our preliminary work [15] (that had two separate tool flows), modifications were made to both the LegUp and ODIN-II tools so that CHStone benchmarks could be carried through the typical full VTR flow (ODIN-II, ABC, VPR) using ODIN-II for front-end synthesis. In the preliminary work [15], Altera Quartus II is used for the front-end synthesis thus producing an Altera-specific mapping for DSP blocks, Memory blocks, and Carry Chains-all of which are not supported by the standard VPR architectures. This restricted us only to be able to make post-mapping estimates.…”

“…3) A full post-place-and-route architecture evaluation with VTR7 [1], and CHStone [2] benchmarks facilitated by LegUp-HLS [3], the Verilog-to-Routing project [1] showing impact on both area and delay. Compared with the preliminary publication [15], we have performed transistor level modelling of the MUX4 LE, further studied the fracturable architectures, and unified the open source tool-flow from C through LegUp-HLS to the VTR flow. Sparse crossbars (versus full crossbars in the previous work) have also been included in our CLBs, increasing modelling accuracy.…”

Technology Mapping into General Programmable Cells

“…For example, LUT structures combine two or more LUTs in one cell [5] [17]. Other extensions include cells based on LUTs and AND gates [1], LUTs and MUXes [4] [16], and cones of elementary gates [20].…”