A Case Study of Side-Channel Analysis Using Decoupling Capacitor Power Measurement with the OpenADC

O’Flynn, Colin; Chen, Zhizhang

doi:10.1007/978-3-642-37119-6_22

Cited by 13 publications

(3 citation statements)

References 14 publications

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“…Synchronous sampling has already been demonstrated to be a useful tool in reducing the data complexity when working with side-channel analysis measurements [10,12,13]. It is know that compression of the power traces can be performed post-capture to reduce them to points of interest.…”

Section: Discussionmentioning

confidence: 99%

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Synchronous sampling and clock recovery of internal oscillators for side channel analysis and fault injection

O’Flynn

Chen

2014

J Cryptogr Eng

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Measuring power consumption for side channel analysis typically uses an oscilloscope, which measures the data relative to an internal sample clock. By synchronizing the sampling clock to the clock of the target device, the sample rate requirements are considerably relaxed; the attack will succeed with a much lower sample rate.This work characterizes the performance of a synchronous sampling system attacking a modern microcontroller running a software AES implementation. This attack is characterized under four conditions: with a stable crystal-oscillator based clock, with a clock that is randomly varied between 3.9 MHz-13 MHz, with an internal oscillator that is randomly varied between 7.2 MHz-8.1 MHz, and with an internal oscillator that has slight random variation due to natural 'drift' in the oscillator.Traces captured with the synchronous sampling technique can be processed with a standard Differential Power Analysis (DPA) style attack in all four cases, whereas when an oscilloscope is used only the stable oscillator setup is successful. This work also develops the hardware to recover the internal clock of a device which does not have an externally available clock. It is possible to implement this scheme in software only, allowing it to work with existing oscilloscope-based test environments.Performing the recovery in hardware allows the use of fault injection with excellent temporal stability relative to a sensitive event. This is demonstrated with a power glitch inserted into a microcontroller, where the glitch is triggered based on a signature in the measured power consumption.

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Section: Discussionmentioning

confidence: 99%

“…The application of this to side-channel analysis was first described in Section 5.2 of [10]. A demonstration of this technique to attack the SASEBO-GII board is given in [12], where sampling at 96 MS/s synchronously achieves similar results to 2 GS/s asynchronously.…”

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confidence: 94%

Synchronous sampling and clock recovery of internal oscillators for side channel analysis and fault injection

O’Flynn

Chen

2014

J Cryptogr Eng

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“…Synchronous sampling, a technique that collects traces while synchronizing the sample clock to the device clock, is useful for SCA [25]. It was reported in [24] that the results of a CPA attack using traces collected by synchronous sampling are similar to those of traces collected asynchronously at a high sampling rate. O'Flynn and Chen [26] showed that increasing the sampling rate does not improve the CPA attack results and demonstrated the enhancement of the CPA results when using traces collected by synchronous sampling.…”

Section: Related Work For Synchronous Samplingmentioning

confidence: 99%

Synchronous Real-Time Sampling Technique for Side-Channel Analysis Against Randomly Varying Clock-Based Countermeasures

2021

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Power analysis attacks pose a significant threat to the security of cryptographic devices as they can reveal a secret key. Performing cryptographic operations based on a randomly varying clock (RVC) is a practical countermeasure against such attacks. The countermeasure makes it difficult to align power traces, which is a prerequisite for power analysis attacks to succeed. This paper introduces a synchronous real-time sampling (SRTS) technique as an advanced hardware-implemented approach to collect traces for a power analysis attack that negates countermeasures involving practical RVCs. By recovering the RVC, the leakage signal corresponding to the recovered clock edge is synchronously sampled in real time. We propose an analog-based hardware system implemented with two circuit blocks for SRTS operations, namely, a clock recovery block and an analog signal-processing block. The target of the power analysis attack is an Advanced Encryption Standard (AES)-128 software-implemented smart card operated at 20 MHz, which is varied in the range of 30% by the RVC countermeasure. The traces captured by the SRTS show that the suboperations of the AES encryption are distinct in contrast to the indistinguishable waveforms captured at a fixed sample rate. The results of the power analysis attack demonstrate that the correct key is successfully extracted with a high correlation coefficient at the S-box output of the AES. The proposed SRTS method improves the relative distinguishing margin by 191.4% and reduces the required number of traces to 2.75% compared with the conventional correlation power analysis attack with a fixed sample clock. INDEX TERMS Alignment, power analysis attack, randomly varying clock, side-channel analysis, smart card, synchronous real-time sampling

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Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration

Ali

Hettwer

Karimov

et al. 2021

Lecture Notes in Computer Science

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A Case Study of Side-Channel Analysis Using Decoupling Capacitor Power Measurement with the OpenADC

Cited by 13 publications

References 14 publications

Synchronous sampling and clock recovery of internal oscillators for side channel analysis and fault injection

Synchronous sampling and clock recovery of internal oscillators for side channel analysis and fault injection

Synchronous Real-Time Sampling Technique for Side-Channel Analysis Against Randomly Varying Clock-Based Countermeasures

Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration

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