A cellular processor array simulation and hardware prototyping tool

Barr, David R. W.; Dudek, Piotr

doi:10.1109/cnna.2008.4588680

Cited by 2 publications

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“…Further to this, many CPAs require additional interfaces and control systems which are specifically built for the device, introducing additional design costs and possibly restricting the performance of the overall CPA system. This paper is an extended version of work presented in [18] and presents APRON (Array Processing enviRONment), a high-speed, flexible, and virtual CPA implemented entirely in software. The software fulfils two objectives: firstly to provide an extensible, customisable implementation of a general purpose array processing engine, which is a basis for the design and "virtual prototyping" of new CPAs; secondly to provide a high-speed emulation of any CPA-based device, allowing the user to design pixel-parallel image processing algorithms and explore multilayer neural networks, cellular automata, and other phenomena related to CPAs, with a variety of tools for data analysis, performance evaluation, and algorithm development.…”

Section: Introductionmentioning

confidence: 99%

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

Barr

Dudek

2009

EURASIP J. Adv. Signal Process.

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We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

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Section: Introductionmentioning

confidence: 99%

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

Barr

Dudek

2009

EURASIP J. Adv. Signal Process.

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“…APRON (Array Processing enviRONment) is a flexible, processor array design and simulation tool [3], which has been optimised for high speed and accuracy on a standard desktop computer. This demonstration will show the APRON system performing a variety of algorithms, with a bias towards vision system emulation.…”

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confidence: 99%

Demonstration of the APRON processor array simulation software

Barr

Dudek

2008

2008 11th International Workshop on Cellular Neural Networks and Their Applications

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A software tool for the development, prototyping and emulation of cellular processor array hardware is presented. APRON provides a 'virtual processor array' that operates at high speed, that can be extended to form vision systems, multi-layer neural networks, cellular neural networks and neuromorphic arrays. SUMMARYCellular Processor Arrays (CPAs) like those in [1,2] implement a high-density grid of computationally simple processors, with local memories, and neighbourhood communication, operating under the Single Instruction Multiple Data (SIMD) paradigm. This arrangement has proven to be particularly suited to pixel-parallel image processing, cellular neural networks (CNNs), multi-layer neural networks, neuromorphic arrays, and computational neuroscience models. This suitability is largely due to the elimination of any memory access bottlenecks, traditionally associated with serial implementations of the same applications, and specifically designed functional components within the processors. The field of CPA related research has been growing steadily, therefore so has the development of new hardware.We have developed a software system that can be used at all stages in the lifecycle of a CPA device. APRON (Array Processing enviRONment) is a flexible, processor array design and simulation tool [3], which has been optimised for high speed and accuracy on a standard desktop computer. This demonstration will show the APRON system performing a variety of algorithms, with a bias towards vision system emulation. Through the use of a webcam, images are captured and processed fast-enough to result in an interactive simulation. Figure 1 shows the APRON software executing several algorithms: a) The APRON IDE, b) Hole-Filling using the CNN paradigm, c) Retina Vessel Extraction using Pixel Level Snakes [4], d) biologically plausible excitable medium using Izhikevich neurons and a probabilistic Gaussian connectivity strategy, e) Greenberg-Hastings cellular Automata, f) Half-toning using CNN in real-time, g) Salient feature extraction in real-time, h) Multi-layer model of Intrinsic Basal Ganglia [5]. We also show how the software can be used as a hardware prototyping tool and CPA development environment, implementing as an example the ASPA [1] architecture and its instruction set.

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A cellular processor array simulation and hardware prototyping tool

Cited by 2 publications

References 10 publications

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

Demonstration of the APRON processor array simulation software

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