A Chaotic Time-Delay Sampled-Data System and Its Implementation

Abstract

Chaotic time-delay systems are attractive candidates to generate chaotic dynamics because of their relatively simple system model. The circuit realization of the time-delay part is the main drawback of these systems. In order to overcome this drawback, a chaotic time-delay system which features a binary feedback function is presented. The use of binary feedback function results in a considerably simplified implementation of the time-delay unit based on using a flip-flop chain. Modeling the system thus obtained yields a chaotic sampled-data system. The existence of chaotic dynamics in the introduced sampled-data systems is numerically verified by calculating system Lyapunov exponents and applying a detailed bifurcation analysis. The chaotic attractor of the introduced sampled-data system is verified by the circuit realization of the system. In order to minimize the number of flip-flops in the chain while keeping the system in chaos, the spectrum of Lyapunov exponent versus clock frequency of the flip-flops and a bifurcation parameter is computed. The circuit realization of the introduced sampled-data system includes a relatively simple structure compared to other chaotic time-delay systems and this overcomes the complexity of the circuit implementation of the time-delay block.

Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit

“…The circuit configuration (component values and parameters) are also found in Figure 12. The delay line works properly, and the same chaotic behavior in [10] is observed. Figure 13a shows the phase portrait of the original system with flip-flop chain, and Figure 13b shows the phase portrait of the system with the proposed ADD-based delay line [10].…”

“…If all logical resources of the target FPGA is occupied by this 34-LUT configuration and if they are connected in cascaded form, 1.71 ms total amount of delay is achieved, which is already impossible with pure buffer chain. The ADD design is tested within a time-delay sampled-data feedback system [10] in which the delay line on the feedback is implemented by a D-type flip-flop chain that functions as a sample-and-hold block. This delay line in [10] is swapped with a cascaded 152 pieces of ninth-order recursive ADD blocks.…”

Multi‐scroll chaotic attractors from a generalized time‐delay sampled‐data system

“…The original chaotic system has been proposed in as a time‐delay sampled‐data system. The mathematical model of the original system is given by where t k is the k ‐th sampling time, T s is the sampling period, τ is the delay, and α is a bifurcation parameter.…”

“…In the latter example, a true random bit generation has been experimentally demonstrated using the circuit in . Even better throughput is recorded using two combined circuits by Yeniceri et al in 2013 . The motivating work that proves that the entropy of a random number generator increases using multi‐scroll chaotic attractors encourages the application‐centric research on multi‐scroll generators.…”

“…The motivating work that proves that the entropy of a random number generator increases using multi‐scroll chaotic attractors encourages the application‐centric research on multi‐scroll generators. This paper proposes a generalization for the time‐delay sampled‐data chaotic system in with an efficient delay‐line solution in order to generate multi‐scroll attractor. In Section 2, time‐delay sampled‐data chaotic system is explored.…”