A Characterization of Scalable Shared Memories

Kohli, Prince; Neiger, Gil; Ahamad, Mustaque

doi:10.1109/icpp.1993.15

Cited by 17 publications

(10 citation statements)

References 14 publications

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“…Slow memory given by Hutto and Ahamad [21] can also be defined using this formalism, as can processor consistency [-4, 16, 18]. We are currently exploring the use of this formalism in the definition of other memories [25].…”

Section: Shared Memory Systemsmentioning

confidence: 98%

Causal memory: definitions, implementation, and programming

et al. 1995

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Tech. His current research interests include distributed shared memories and distributed operating systems. He has worked on formal characterizations of various classes of shared memories and their implementations on workstation clusters.Summary. The abstraction of a shared m e m o r y is of growing i m p o r t a n c e in distributed c o m p u t i n g systems. Traditional m e m o r y consistency ensures that ali processes agree on a c o m m o n order of all operations on memory. Unfortunately, providing these guarantees entaits access latencies that prevent scaling to large systems. This paper weakens such guarantees by defining causal memory, an abstraction that ensures that processes in a system agree on the relative ordering ,:s operations that are causally related. Because causal m e m o r y is weakly consistent, it admits more executions, and hence m o r e concurrency, t h a n either 38 atomic or sequentially consistent memories. This paper provides a formal definition of causal memory and gives an implementation for message-passing systems. In addition, it describes a practical class of programs that, if developed for a strongly consistent memory, run correctly with causal memory.

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Section: Shared Memory Systemsmentioning

confidence: 98%

Causal memory: definitions, implementation, and programming

et al. 1995

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“…in the ARM, IBM POWER, Itanium, MIPS, Sparc, and x86 architectures. This has prompted much research into the semantics that multiprocessors could or actually do provide, including [2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40]. Recent work among this has established semantic models for x86 [32], IBM POWER [33,34,35,36,38], and ARM [39] that are validated both by experiment against multiprocessor implementations and by discussion with the vendor architects.…”

Section: Introductionmentioning

confidence: 99%

Mixed-size concurrency: ARM, POWER, C/C++11, and SC

et al. 2017

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“…Memory coherence only specifies the properties of a single memory location, while a memory consistency model [12] is needed to specify the relationship between reads and writes to different locations and more exactly determine the value returned by the read operation. Given the wide variation in consistency models in processors [1,9,15], it seems imprudent to assume a stronger consistency model than weak ordering unless necessary. Informally, weak ordering allows us to assume that DCAS and gAS are linearizable primitives with respect to each other, and, further, act as barriers for read and write.…”

Section: Dcasmentioning

confidence: 99%

Two-handed emulation

Greenwald

2002

Proceedings of the Twenty-First Annual Symposium on Principles of Distributed Computing

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This paper partly addresses the question of whether, in principle, there is any point in adding richer hardware synchronization primitives when the existing set is "universal", and therefore sufficient to synchronize any data structure in a non-blocking manner. The context of this paper is the ongoing investigation of the utility of adding a DCAS instruction to modern processors to aid the design and performance of non-blocking algorithms. We add one more piece of evidence in support of this instruction.In particular, we demonstrate that DCAS is sufficient to enable a technique called "two-handed emulation" which yields efficient and understandable implementations of a class of data structures. We present a non-blocking implementation of a doubly-linked list to show the basic technique. We describe a non-blocking implementation of a dynamically resizable hash-table to illustrate how the technique is amenable to optimizations that improve performance and increase concurrency. -485-1/02/0007...$5.00.crease total system throughput.Nevertheless, non-blocking algorithms have not been widely deployed in practice outside of a select group of data structures (for example FIFO queues [18], deques [3], counters, stacks [20], and others). Two impediments block the widespread use of NBS: conceptual complexity and poor performance in the common case.

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A Characterization of Scalable Shared Memories

Cited by 17 publications

References 14 publications

Causal memory: definitions, implementation, and programming

Causal memory: definitions, implementation, and programming

Mixed-size concurrency: ARM, POWER, C/C++11, and SC

Two-handed emulation

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